* [U-Boot] Adds driver for Xilinx' xps_spi SPI controller
@ 2010-07-27 13:56 Graeme Smecher
2010-07-27 13:56 ` [U-Boot] [PATCH] " Graeme Smecher
0 siblings, 1 reply; 6+ messages in thread
From: Graeme Smecher @ 2010-07-27 13:56 UTC (permalink / raw)
To: u-boot
Adds a driver for Xilinx' xps_spi controller. This code differs in only trivial
ways from the altera_spi driver. It plays nice with Thomas Chou's mmc_spi
driver, as well as with SPI flash.
Documentation for the SPI core is available here:
http://www.xilinx.com/support/documentation/ip_documentation/xps_spi.pdf
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller
2010-07-27 13:56 [U-Boot] Adds driver for Xilinx' xps_spi SPI controller Graeme Smecher
@ 2010-07-27 13:56 ` Graeme Smecher
2010-07-27 14:02 ` Graeme Smecher
0 siblings, 1 reply; 6+ messages in thread
From: Graeme Smecher @ 2010-07-27 13:56 UTC (permalink / raw)
To: u-boot
---
drivers/spi/Makefile | 1 +
drivers/spi/xilinx_spi.c | 171 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 172 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/xilinx_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index dfcbb8b..34e0f31 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libspi.a
COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
+COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
new file mode 100644
index 0000000..99ce661
--- /dev/null
+++ b/drivers/spi/xilinx_spi.c
@@ -0,0 +1,171 @@
+/*
+ * Xilinx SPI driver
+ *
+ * based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
+ * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <spi.h>
+
+#define debug printf
+
+#define XILINX_SPI_RR 0x6c
+#define XILINX_SPI_TR 0x68
+#define XILINX_SPI_SR 0x64
+#define XILINX_SPI_CR 0x60
+#define XILINX_SPI_SSR 0x70
+
+#define XILINX_SPI_SR_RX_EMPTY_MSK 0x01
+
+#define XILINX_SPI_CR_DEFAULT (0x0086)
+
+#if XPAR_XSPI_NUM_INSTANCES > 4
+# warning "The xilinx_spi driver will ignore some of your SPI peripherals!"
+#endif
+
+static ulong xilinx_spi_base_list[] = {
+#ifdef XPAR_SPI_0_BASEADDR
+ XPAR_SPI_0_BASEADDR,
+#endif
+#ifdef XPAR_SPI_1_BASEADDR
+ XPAR_SPI_1_BASEADDR,
+#endif
+#ifdef XPAR_SPI_2_BASEADDR
+ XPAR_SPI_2_BASEADDR,
+#endif
+#ifdef XPAR_SPI_3_BASEADDR
+ XPAR_SPI_3_BASEADDR,
+#endif
+};
+
+struct xilinx_spi_slave {
+ struct spi_slave slave;
+ ulong base;
+};
+#define to_xilinx_spi_slave(s) container_of(s, struct xilinx_spi_slave, slave)
+
+__attribute__((weak))
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
+}
+
+__attribute__((weak))
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ writel(~(1 << slave->cs), xilspi->base + XILINX_SPI_SSR);
+}
+
+__attribute__((weak))
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ writel(~0, xilspi->base + XILINX_SPI_SSR);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct xilinx_spi_slave *xilspi;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ xilspi = malloc(sizeof(*xilspi));
+ if (!xilspi)
+ return NULL;
+
+ xilspi->slave.bus = bus;
+ xilspi->slave.cs = cs;
+ xilspi->base = xilinx_spi_base_list[bus];
+ debug("%s: bus:%i cs:%i base:%lx\n", __func__,
+ bus, cs, xilspi->base);
+
+ writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR);
+
+ return &xilspi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ free(xilspi);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+ writel(~0, xilspi->base + XILINX_SPI_SSR);
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+ writel(~0, xilspi->base + XILINX_SPI_SSR);
+}
+
+#ifndef CONFIG_XILINX_SPI_IDLE_VAL
+# define CONFIG_XILINX_SPI_IDLE_VAL 0xff
+#endif
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ /* assume spi core configured to do 8 bit transfers */
+ uint bytes = bitlen / 8;
+ const uchar *txp = dout;
+ uchar *rxp = din;
+
+ debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
+ slave->bus, slave->cs, bitlen, bytes, flags);
+ if (bitlen == 0)
+ goto done;
+
+ if (bitlen % 8) {
+ flags |= SPI_XFER_END;
+ goto done;
+ }
+
+ /* empty read buffer */
+ while (!(readl(xilspi->base + XILINX_SPI_SR) &
+ XILINX_SPI_SR_RX_EMPTY_MSK))
+ readl(xilspi->base + XILINX_SPI_RR);
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ while (bytes--) {
+ uchar d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+ debug("%s: tx:%x ", __func__, d);
+ writel(d, xilspi->base + XILINX_SPI_TR);
+ while (readl(xilspi->base + XILINX_SPI_SR) &
+ XILINX_SPI_SR_RX_EMPTY_MSK)
+ ;
+ d = readl(xilspi->base + XILINX_SPI_RR);
+ if (rxp)
+ *rxp++ = d;
+ debug("rx:%x\n", d);
+ }
+ done:
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
--
1.6.3.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller
2010-07-27 13:56 ` [U-Boot] [PATCH] " Graeme Smecher
@ 2010-07-27 14:02 ` Graeme Smecher
0 siblings, 0 replies; 6+ messages in thread
From: Graeme Smecher @ 2010-07-27 14:02 UTC (permalink / raw)
To: u-boot
Hi all,
I neglected to point out that this driver has been tested with Thomas
Chou's mmc_spi patches, and appears to work with SPI flash (Winbond
w25q64) as well.
A quick diff shows this driver is nearly identical to the altera_spi
driver. The only differences are:
* the CS register is active-low here, and
* the control register requires some additional setup.
cheers,
Graeme Smecher
On 10-07-27 09:56 AM, Graeme Smecher wrote:
> ---
> drivers/spi/Makefile | 1 +
> drivers/spi/xilinx_spi.c | 171 ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 172 insertions(+), 0 deletions(-)
> create mode 100644 drivers/spi/xilinx_spi.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index dfcbb8b..34e0f31 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
> LIB := $(obj)libspi.a
>
> COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
> +COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
> COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
> diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
> new file mode 100644
> index 0000000..99ce661
> --- /dev/null
> +++ b/drivers/spi/xilinx_spi.c
> @@ -0,0 +1,171 @@
> +/*
> + * Xilinx SPI driver
> + *
> + * based on bfin_spi.c, by way of altera_spi.c
> + * Copyright (c) 2005-2008 Analog Devices Inc.
> + * Copyright (c) 2010 Thomas Chou<thomas@wytron.com.tw>
> + * Copyright (c) 2010 Graeme Smecher<graeme.smecher@mail.mcgill.ca>
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +#include<common.h>
> +#include<asm/io.h>
> +#include<malloc.h>
> +#include<spi.h>
> +
> +#define debug printf
> +
> +#define XILINX_SPI_RR 0x6c
> +#define XILINX_SPI_TR 0x68
> +#define XILINX_SPI_SR 0x64
> +#define XILINX_SPI_CR 0x60
> +#define XILINX_SPI_SSR 0x70
> +
> +#define XILINX_SPI_SR_RX_EMPTY_MSK 0x01
> +
> +#define XILINX_SPI_CR_DEFAULT (0x0086)
> +
> +#if XPAR_XSPI_NUM_INSTANCES> 4
> +# warning "The xilinx_spi driver will ignore some of your SPI peripherals!"
> +#endif
> +
> +static ulong xilinx_spi_base_list[] = {
> +#ifdef XPAR_SPI_0_BASEADDR
> + XPAR_SPI_0_BASEADDR,
> +#endif
> +#ifdef XPAR_SPI_1_BASEADDR
> + XPAR_SPI_1_BASEADDR,
> +#endif
> +#ifdef XPAR_SPI_2_BASEADDR
> + XPAR_SPI_2_BASEADDR,
> +#endif
> +#ifdef XPAR_SPI_3_BASEADDR
> + XPAR_SPI_3_BASEADDR,
> +#endif
> +};
> +
> +struct xilinx_spi_slave {
> + struct spi_slave slave;
> + ulong base;
> +};
> +#define to_xilinx_spi_slave(s) container_of(s, struct xilinx_spi_slave, slave)
> +
> +__attribute__((weak))
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> + return bus< ARRAY_SIZE(xilinx_spi_base_list)&& cs< 32;
> +}
> +
> +__attribute__((weak))
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
> + writel(~(1<< slave->cs), xilspi->base + XILINX_SPI_SSR);
> +}
> +
> +__attribute__((weak))
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
> + writel(~0, xilspi->base + XILINX_SPI_SSR);
> +}
> +
> +void spi_init(void)
> +{
> +}
> +
> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> + unsigned int max_hz, unsigned int mode)
> +{
> + struct xilinx_spi_slave *xilspi;
> +
> + if (!spi_cs_is_valid(bus, cs))
> + return NULL;
> +
> + xilspi = malloc(sizeof(*xilspi));
> + if (!xilspi)
> + return NULL;
> +
> + xilspi->slave.bus = bus;
> + xilspi->slave.cs = cs;
> + xilspi->base = xilinx_spi_base_list[bus];
> + debug("%s: bus:%i cs:%i base:%lx\n", __func__,
> + bus, cs, xilspi->base);
> +
> + writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR);
> +
> + return&xilspi->slave;
> +}
> +
> +void spi_free_slave(struct spi_slave *slave)
> +{
> + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
> + free(xilspi);
> +}
> +
> +int spi_claim_bus(struct spi_slave *slave)
> +{
> + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
> +
> + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
> + writel(~0, xilspi->base + XILINX_SPI_SSR);
> + return 0;
> +}
> +
> +void spi_release_bus(struct spi_slave *slave)
> +{
> + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
> +
> + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
> + writel(~0, xilspi->base + XILINX_SPI_SSR);
> +}
> +
> +#ifndef CONFIG_XILINX_SPI_IDLE_VAL
> +# define CONFIG_XILINX_SPI_IDLE_VAL 0xff
> +#endif
> +
> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> + void *din, unsigned long flags)
> +{
> + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
> + /* assume spi core configured to do 8 bit transfers */
> + uint bytes = bitlen / 8;
> + const uchar *txp = dout;
> + uchar *rxp = din;
> +
> + debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
> + slave->bus, slave->cs, bitlen, bytes, flags);
> + if (bitlen == 0)
> + goto done;
> +
> + if (bitlen % 8) {
> + flags |= SPI_XFER_END;
> + goto done;
> + }
> +
> + /* empty read buffer */
> + while (!(readl(xilspi->base + XILINX_SPI_SR)&
> + XILINX_SPI_SR_RX_EMPTY_MSK))
> + readl(xilspi->base + XILINX_SPI_RR);
> +
> + if (flags& SPI_XFER_BEGIN)
> + spi_cs_activate(slave);
> +
> + while (bytes--) {
> + uchar d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
> + debug("%s: tx:%x ", __func__, d);
> + writel(d, xilspi->base + XILINX_SPI_TR);
> + while (readl(xilspi->base + XILINX_SPI_SR)&
> + XILINX_SPI_SR_RX_EMPTY_MSK)
> + ;
> + d = readl(xilspi->base + XILINX_SPI_RR);
> + if (rxp)
> + *rxp++ = d;
> + debug("rx:%x\n", d);
> + }
> + done:
> + if (flags& SPI_XFER_END)
> + spi_cs_deactivate(slave);
> +
> + return 0;
> +}
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller.
@ 2010-08-03 15:47 Graeme Smecher
2010-08-03 17:59 ` Mike Frysinger
0 siblings, 1 reply; 6+ messages in thread
From: Graeme Smecher @ 2010-08-03 15:47 UTC (permalink / raw)
To: u-boot
This code differs in only trivial ways from the altera_spi driver. It plays
nice with Thomas Chou's mmc_spi driver, as well as with SPI flash.
Documentation for the SPI core is available here:
http://www.xilinx.com/support/documentation/ip_documentation/xps_spi.pdf
Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
---
drivers/spi/Makefile | 1 +
drivers/spi/xilinx_spi.c | 173 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 174 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/xilinx_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index dfcbb8b..34e0f31 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libspi.a
COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
+COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
new file mode 100644
index 0000000..bda7c5b
--- /dev/null
+++ b/drivers/spi/xilinx_spi.c
@@ -0,0 +1,173 @@
+/*
+ * Xilinx SPI driver
+ *
+ * based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
+ * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <spi.h>
+
+#define XILINX_SPI_RR 0x6c
+#define XILINX_SPI_TR 0x68
+#define XILINX_SPI_SR 0x64
+#define XILINX_SPI_CR 0x60
+#define XILINX_SPI_SSR 0x70
+
+#define XILINX_SPI_SR_RX_EMPTY_MSK 0x01
+
+#define XILINX_SPI_CR_DEFAULT (0x0006)
+#define XILINX_SPI_CR_MSS_MSK (0x0080)
+
+#if XPAR_XSPI_NUM_INSTANCES > 4
+# warning "The xilinx_spi driver will ignore some of your SPI peripherals!"
+#endif
+
+static ulong xilinx_spi_base_list[] = {
+#ifdef XPAR_SPI_0_BASEADDR
+ XPAR_SPI_0_BASEADDR,
+#endif
+#ifdef XPAR_SPI_1_BASEADDR
+ XPAR_SPI_1_BASEADDR,
+#endif
+#ifdef XPAR_SPI_2_BASEADDR
+ XPAR_SPI_2_BASEADDR,
+#endif
+#ifdef XPAR_SPI_3_BASEADDR
+ XPAR_SPI_3_BASEADDR,
+#endif
+};
+
+struct xilinx_spi_slave {
+ struct spi_slave slave;
+ ulong base;
+};
+#define to_xilinx_spi_slave(s) container_of(s, struct xilinx_spi_slave, slave)
+
+__attribute__((weak))
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
+}
+
+__attribute__((weak))
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ writel(~(1 << slave->cs), xilspi->base + XILINX_SPI_SSR);
+ writel(XILINX_SPI_CR_DEFAULT | XILINX_SPI_CR_MSS_MSK,
+ xilspi->base + XILINX_SPI_CR);
+}
+
+__attribute__((weak))
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+ writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR);
+ writel(~0, xilspi->base + XILINX_SPI_SSR);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct xilinx_spi_slave *xilspi;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ xilspi = malloc(sizeof(*xilspi));
+ if (!xilspi)
+ return NULL;
+
+ xilspi->slave.bus = bus;
+ xilspi->slave.cs = cs;
+ xilspi->base = xilinx_spi_base_list[bus];
+ debug("%s: bus:%i cs:%i base:%lx\n", __func__,
+ bus, cs, xilspi->base);
+
+ return &xilspi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ free(xilspi);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+ writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR);
+ writel(~0, xilspi->base + XILINX_SPI_SSR);
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+ writel(~0, xilspi->base + XILINX_SPI_SSR);
+}
+
+#ifndef CONFIG_XILINX_SPI_IDLE_VAL
+# define CONFIG_XILINX_SPI_IDLE_VAL 0xff
+#endif
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ /* assume spi core configured to do 8 bit transfers */
+ uint bytes = bitlen / 8;
+ const uchar *txp = dout;
+ uchar *rxp = din;
+
+ debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
+ slave->bus, slave->cs, bitlen, bytes, flags);
+ if (bitlen == 0)
+ goto done;
+
+ if (bitlen % 8) {
+ flags |= SPI_XFER_END;
+ goto done;
+ }
+
+ /* empty read buffer */
+ while (!(readl(xilspi->base + XILINX_SPI_SR) &
+ XILINX_SPI_SR_RX_EMPTY_MSK))
+ readl(xilspi->base + XILINX_SPI_RR);
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ while (bytes--) {
+ uchar d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+ debug("%s: tx:%x ", __func__, d);
+ writel(d, xilspi->base + XILINX_SPI_TR);
+ while (readl(xilspi->base + XILINX_SPI_SR) &
+ XILINX_SPI_SR_RX_EMPTY_MSK)
+ ;
+ d = readl(xilspi->base + XILINX_SPI_RR);
+ if (rxp)
+ *rxp++ = d;
+ debug("rx:%x\n", d);
+ }
+ done:
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
--
1.6.3.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller.
2010-08-03 15:47 Graeme Smecher
@ 2010-08-03 17:59 ` Mike Frysinger
2010-08-04 21:01 ` Graeme Smecher
0 siblings, 1 reply; 6+ messages in thread
From: Mike Frysinger @ 2010-08-03 17:59 UTC (permalink / raw)
To: u-boot
On Tuesday, August 03, 2010 11:47:42 Graeme Smecher wrote:
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
>
> COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
> +COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
this is a sorted list. please keep it that way
> --- /dev/null
> +++ b/drivers/spi/xilinx_spi.c
>
> +static ulong xilinx_spi_base_list[] = {
> +#ifdef XPAR_SPI_0_BASEADDR
> + XPAR_SPI_0_BASEADDR,
> +#endif
> +#ifdef XPAR_SPI_1_BASEADDR
> + XPAR_SPI_1_BASEADDR,
> +#endif
> +#ifdef XPAR_SPI_2_BASEADDR
> + XPAR_SPI_2_BASEADDR,
> +#endif
> +#ifdef XPAR_SPI_3_BASEADDR
> + XPAR_SPI_3_BASEADDR,
> +#endif
> +};
if this is only ever read, you might want to declare it const so it ends up in
the rodata section.
what if someone defines just XPAR_SPI_3_BASEADDR ? do you want to be
consistent in bus id 3 always corresponds to XPAR_SPI_3_BASEADDR ? or are you
OK with the numbers always being relative ? doesnt matter to me, just
highlighting some things that might have been missed.
-mike
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller.
2010-08-03 17:59 ` Mike Frysinger
@ 2010-08-04 21:01 ` Graeme Smecher
0 siblings, 0 replies; 6+ messages in thread
From: Graeme Smecher @ 2010-08-04 21:01 UTC (permalink / raw)
To: u-boot
Hi Mike,
Thanks again for reviewing! Comments in-line; an updated patch will follow.
On 03/08/10 10:59 AM, Mike Frysinger wrote:
> On Tuesday, August 03, 2010 11:47:42 Graeme Smecher wrote:
>
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>>
>> COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
>> +COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>> COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>>
> this is a sorted list. please keep it that way
>
Whoops -- OK.
>> --- /dev/null
>> +++ b/drivers/spi/xilinx_spi.c
>>
>> +static ulong xilinx_spi_base_list[] = {
>> +#ifdef XPAR_SPI_0_BASEADDR
>> + XPAR_SPI_0_BASEADDR,
>> +#endif
>> +#ifdef XPAR_SPI_1_BASEADDR
>> + XPAR_SPI_1_BASEADDR,
>> +#endif
>> +#ifdef XPAR_SPI_2_BASEADDR
>> + XPAR_SPI_2_BASEADDR,
>> +#endif
>> +#ifdef XPAR_SPI_3_BASEADDR
>> + XPAR_SPI_3_BASEADDR,
>> +#endif
>> +};
>>
> if this is only ever read, you might want to declare it const so it ends up in
> the rodata section.
>
Done.
> what if someone defines just XPAR_SPI_3_BASEADDR ? do you want to be
> consistent in bus id 3 always corresponds to XPAR_SPI_3_BASEADDR ? or are you
> OK with the numbers always being relative ? doesnt matter to me, just
> highlighting some things that might have been missed.
>
These numbers come from autogenerated headers and are (as far as I know)
always numbered from 0. Offhand, the above code seems like the least
confusing approach. I don't have a particularly strong opinion either.
cheers,
Graeme
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2010-08-04 21:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2010-07-27 13:56 [U-Boot] Adds driver for Xilinx' xps_spi SPI controller Graeme Smecher
2010-07-27 13:56 ` [U-Boot] [PATCH] " Graeme Smecher
2010-07-27 14:02 ` Graeme Smecher
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2010-08-03 15:47 Graeme Smecher
2010-08-03 17:59 ` Mike Frysinger
2010-08-04 21:01 ` Graeme Smecher
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