[U-Boot] How to support Page Mode Flash Memory Device?

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Cheng,

> But i consider that the "write buffer" and the "page mode read"
> are quite different. BTW, i have searched the internet but got
> nothing about Page Mode source code. Has anyone ever implemented it?

There is nothing to 'implement'. Page mode flash has a
timing parameter indicating the time to the first read,
and then the time for subsequent reads within a page
to return.

If you are interfacing to this flash using a processor
local bus controller, then you generally only have one
read timing parameter you can configure. In that case,
you would have to configure the local bus controller
read timing of the processor to the flash worst-case
value, i.e., the timing for the read of the first word
in a page.

If you are interfacing to the flash using an FPGA, then
you can exploit this feature. For example, I use this
feature to get optimal read timing from a FPGA configuration
controller.

See p30, Figure 12.

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

That figure should clarify what page mode means.
The example design uses S29GL512N11TF020 parts.

Cheers,
Dave