[U-Boot] [PATCH] orion5x: allow overriding default mappings windows

Albert Aribaud
2010-07-13T07:04:26Z

Turn all ORION5X_DEF{ADR,SZ}_xxx macros into ORION5X_{ADR,SZ}_xxx
and allow defining them from board code to override defaults. This
is particularly useful for defining board-specific FLASH address
and size in board header file rather than having to tweak orion5x
code.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
arch/arm/cpu/arm926ejs/orion5x/cpu.c | 40 ++++++------
arch/arm/include/asm/arch-orion5x/cpu.h | 98 ++++++++++++++++++++++++-------
2 files changed, 97 insertions(+), 41 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 03c6d06..a921e98 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -87,56 +87,56 @@ int orion5x_config_adr_windows(void)
(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;

/* Window 0: PCIE MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
ORION5X_WIN_ENABLE), &winregs[0].ctrl);
- writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
- writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
- writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+ writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
+ writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+ writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);

/* Window 1: PCIE IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
ORION5X_WIN_ENABLE), &winregs[1].ctrl);
- writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
- writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
- writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+ writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
+ writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+ writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);

/* Window 2: PCI MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
ORION5X_WIN_ENABLE), &winregs[2].ctrl);
- writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
+ writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);

/* Window 3: PCI IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
ORION5X_WIN_ENABLE), &winregs[3].ctrl);
- writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
+ writel(ORION5X_ADR_PCI_IO, &winregs[3].base);

/* Window 4: DEV_CS0 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
ORION5X_WIN_ENABLE), &winregs[4].ctrl);
- writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
+ writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);

/* Window 5: DEV_CS1 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
ORION5X_WIN_ENABLE), &winregs[5].ctrl);
- writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
+ writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);

/* Window 6: DEV_CS2 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
ORION5X_WIN_ENABLE), &winregs[6].ctrl);
- writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
+ writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);

/* Window 7: BOOT Memory address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[7].ctrl);
- writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
+ writel(ORION5X_ADR_BOOTROM, &winregs[7].base);

return 0;
}
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
index 22e2dd3..80717f8 100644
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ b/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -75,35 +75,91 @@ enum orion5x_cpu_attrib {
};

/*
- * Default Device Address MAP BAR values
+ * Device Address MAP BAR values
+/*
+ * All addresses and sizes not defined by board code
+ * will be given default values here.
*/
-#define ORION5X_DEFADR_PCIE_MEM 0x90000000
-#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000
-#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0
-#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024)

-#define ORION5X_DEFADR_PCIE_IO 0xf0000000
-#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000
-#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0
-#define ORION5X_DEFSZ_PCIE_IO (64*1024)
+#if !defined (ORION5X_ADR_PCIE_MEM)
+#define ORION5X_ADR_PCIE_MEM 0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
+#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
+#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0
+#endif
+
+#if !defined (ORION5X_SZ_PCIE_MEM)
+#define ORION5X_SZ_PCIE_MEM (128*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO)
+#define ORION5X_ADR_PCIE_IO 0xf0000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
+#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
+#define ORION5X_ADR_PCIE_IO_REMAP_HI 0
+#endif
+
+#if !defined (ORION5X_SZ_PCIE_IO)
+#define ORION5X_SZ_PCIE_IO (64*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCI_MEM)
+#define ORION5X_ADR_PCI_MEM 0x98000000
+#endif
+
+#if !defined (ORION5X_SZ_PCI_MEM)
+#define ORION5X_SZ_PCI_MEM (128*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCI_IO)
+#define ORION5X_ADR_PCI_IO 0xf0100000
+#endif
+
+#if !defined (ORION5X_SZ_PCI_IO)
+#define ORION5X_SZ_PCI_IO (64*1024)
+#endif
+
+#if !defined (ORION5X_ADR_DEV_CS0)
+#define ORION5X_ADR_DEV_CS0 0xfa000000
+#endif
+
+#if !defined (ORION5X_SZ_DEV_CS0)
+#define ORION5X_SZ_DEV_CS0 (2*1024*1024)
+#endif

-#define ORION5X_DEFADR_PCI_MEM 0x98000000
-#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024)
+#if !defined (ORION5X_ADR_DEV_CS1)
+#define ORION5X_ADR_DEV_CS1 0xf8000000
+#endif

-#define ORION5X_DEFADR_PCI_IO 0xf0100000
-#define ORION5X_DEFSZ_PCI_IO (64*1024)
+#if !defined (ORION5X_SZ_DEV_CS1)
+#define ORION5X_SZ_DEV_CS1 (32*1024*1024)
+#endif

-#define ORION5X_DEFADR_DEV_CS0 0xfa000000
-#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024)
+#if !defined (ORION5X_ADR_DEV_CS2)
+#define ORION5X_ADR_DEV_CS2 0xfa800000
+#endif

-#define ORION5X_DEFADR_DEV_CS1 0xf8000000
-#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024)
+#if !defined (ORION5X_SZ_DEV_CS2)
+#define ORION5X_SZ_DEV_CS2 (1*1024*1024)
+#endif

-#define ORION5X_DEFADR_DEV_CS2 0xfa800000
-#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
+#if !defined (ORION5X_ADR_BOOTROM)
+#define ORION5X_ADR_BOOTROM 0xFFF80000
+#endif

-#define ORION5X_DEFADR_BOOTROM 0xFFF80000
-#define ORION5X_DEFSZ_BOOTROM (512*1024)
+#if !defined (ORION5X_SZ_BOOTROM)
+#define ORION5X_SZ_BOOTROM (512*1024)
+#endif

/*
* PCIE registers are used for SoC device ID and revision
--
1.6.4.4