[U-Boot] [PATCH] p1022ds: add video support

Timur Tabi
2010-09-02T20:35:19Z

Add support for the DIU controller. If CONFIG_VIDEO is defined, then the
console will appear on a DVI monitor instead of the serial port.

Signed-off-by: Timur Tabi <timur@freescale.com>
---

This patch depends on:

[v3] fsl: refactor MPC8610 and MPC5121 DIU code to use existing bitmap and logo features

board/freescale/p1022ds/Makefile | 2 +
board/freescale/p1022ds/diu.c | 172 ++++++++++++++++++++++++++++++++++++++
include/configs/P1022DS.h | 7 ++-
3 files changed, 180 insertions(+), 1 deletions(-)
create mode 100644 board/freescale/p1022ds/diu.c

diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index 8ede2d6..678eb2a 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -16,6 +16,8 @@ COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o

+COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
new file mode 100644
index 0000000..be6e9a8
--- /dev/null
+++ b/board/freescale/p1022ds/diu.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_FSL_DIU_FB
+
+#include "../common/ngpixis.h"
+#include "../common/fsl_diu_fb.h"
+
+#ifdef CONFIG_VIDEO
+#include <stdio_dev.h>
+#include <video_fb.h>
+#endif
+
+#define PX_BRDCFG0_ELBC_DIU 0x02
+
+#define PX_BRDCFG1_DVIEN 0x80
+#define PX_BRDCFG1_DFPEN 0x40
+#define PX_BRDCFG1_BACKLIGHT 0x20
+#define PX_BRDCFG1_DDCEN 0x10
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_MASK 0x0E000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_MASK 0x01800000
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_MASK 0x00600000
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_MASK 0x00180000
+#define AD_RED_C_SHIFT 19
+#define AD_PALETTE 0x00040000
+#define AD_PIXEL_S_MASK 0x00030000
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_MASK 0x0000F000
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_MASK 0x00000F00
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_MASK 0x000000F0
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_MASK 0x0000000F
+#define AD_COMP_0_SHIFT 0
+
+#define AD_DEFAULT
+static int xres, yres;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ debug("DIU pixval = %lu\n", pixval);
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
+ out_be32(&gur->clkdvdr, temp); /* turn off clock */
+ out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
+}
+
+int p1022ds_diu_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ char *monitor_port;
+ u32 pixel_format;
+ u8 temp;
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ temp = in_8(&pixis->brdcfg1);
+
+ monitor_port = getenv("monitor");
+ if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
+ xres = 1024;
+ yres = 768;
+ /* Enable the DFP port, disable the DVI and the backlight */
+ temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT);
+ temp |= PX_BRDCFG1_DFPEN;
+ } else { /* DVI */
+ xres = 1280;
+ yres = 1024;
+ /* Enable the DVI port, disable the DFP and the backlight */
+ temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+ temp |= PX_BRDCFG1_DVIEN;
+ }
+
+ out_8(&pixis->brdcfg1, temp);
+
+ /*
+ * Route the LAD pins to the DIU. This will disable access to the eLBC,
+ * which means we won't be able to read/write any NOR flash addresses!
+ */
+ out_8(&pixis->brdcfg0, in_8(&pixis->brdcfg0) | PX_BRDCFG0_ELBC_DIU);
+ /* we must do the dummy read from eLBC to sync the write as above */
+ in_8(&pixis->brdcfg0);
+
+ /* Setting PMUXCR to switch to DVI from ELBC */
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ clrsetbits_be32(&gur->pmuxcr, 0xc0000000, 0x40000000);
+ in_be32(&gur->pmuxcr);
+
+ return fsl_diu_init(xres, pixel_format, 0);
+}
+
+#ifdef CONFIG_VIDEO
+
+/*
+ * The Graphic Device
+ */
+static GraphicDevice ctfb;
+
+void *video_hw_init(void)
+{
+ struct fb_info *info;
+
+ if (p1022ds_diu_init() < 0)
+ return NULL;
+
+ /* fill in Graphic device struct */
+ sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", xres, yres, 32, 64, 60);
+
+ ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info);
+ ctfb.winSizeX = xres;
+ ctfb.winSizeY = yres;
+ ctfb.plnSizeX = ctfb.winSizeX;
+ ctfb.plnSizeY = ctfb.winSizeY;
+
+ ctfb.gdfBytesPP = 4;
+ ctfb.gdfIndex = GDF_32BIT_X888RGB;
+
+ ctfb.isaBase = 0;
+ ctfb.pciBase = 0;
+ ctfb.memSize = info->screen_size;
+
+ /* Cursor Start Address */
+ ctfb.dprBase = 0;
+ ctfb.vprBase = 0;
+ ctfb.cprBase = 0;
+
+ return &ctfb;
+}
+
+#endif
+
+#endif
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index dcaca2b..d518c69 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -31,6 +31,7 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_HAS_SERDES /* has SERDES */
+#define CONFIG_FSL_DIU_FB /* Has a DIU video controller */

#define CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS
@@ -181,10 +182,14 @@
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)

/* Video */
-/* #define CONFIG_VIDEO */
+#undef CONFIG_VIDEO
+
#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
#endif

/*
--
1.7.2.1