From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Schwarz Date: Tue, 26 Oct 2010 14:34:57 +0200 Subject: [U-Boot] [PATCH] powerpc: do not fixup NULL ptrs In-Reply-To: <20101025191400.33ABD135DE3@gemini.denx.de> References: <1287049904-18917-1-git-send-email-Joakim.Tjernlund@transmode.se> <20101018203948.676071359B3@gemini.denx.de> <1702240919.111.1287950899754.JavaMail.open-xchange@proteus> <20101024201832.DAF78134F26@gemini.denx.de> <739387466.116.1287952424329.JavaMail.open-xchange@proteus> <4CC58B1B.8040005@matrix-vision.de> <20101025171658.D151C152451@gemini.denx.de> <4CC5C226.8080202@matrix-vision.de> <20101025191400.33ABD135DE3@gemini.denx.de> Message-ID: <4CC6CAF1.1000002@matrix-vision.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de All, > >> Having a look at include/asm/global_data.h gives some 40 ulongs for my >> MPC8377 system. >> Current CONFIG_SYS_GBL_DATA_SIZE= 0x100 which should be enough. >> > Indeed. I was asking because I just discovered that most of the > PowerPC boards are actually broken in this respect - 89 % of them, > 170 out of 191 :-( > > >> The system is still dead after removing the 4 nops after _start. >> actually I'm facing another issue and don't now whether this might be related to this thread or not. Just before relocation in arch/powerpc/lib/board.c the CPU gets a "check stop" followed by reset during "memset()" in line 493. [snip] DRAM: 256 MiB Top of RAM usable for U-Boot at: 10000000 Reserving 341k for U-Boot at: 0ffaa000 Reserving 512k for malloc() at: 0ff29f80 - reset - U-Boot 2010.09-00488-g5edbadb-dirty (Oct 26 2010 - 14:16:00) MPC83XX Reset Status: Check Stop, External/Internal Soft, External/Internal Hard I know that DDR might not be 100% stable but it is basically set up properly. Removing the memset yields the next debug messages before resetting again while setting up SP. Is the DDR required to work 100% for a simple write operation or might there be another problem ? 256MiB DDR is mapped by single BAT and there should be no overlapping BATs either. Any ideas ? -- Regards, Andre MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner