[U-Boot] 36-bit u-boot

[U-Boot] 36-bit u-boot

[Leif Sörman]

I have managed to flashed a 36-bits u-boot to my p4080 board.

I have put in two 4Gb dimm into the board but it doesn't work.

I got the following from u-boot.

 

""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""

U-Boot 2009.06-rc1 (Sep 23 2010 - 11:14:44)

 

CPU0:  p4080E, Version: 1.0, (0x82080010)

Core:  E500MC, Version: 1.0, (0x80230010) Clock Configuration:

       CPU0:1199.988 MHz, CPU1:1199.988 MHz, CPU2:1199.988 MHz, CPU3:1199.988 MHz, 

       CPU4:1199.988 MHz, CPU5:1199.988 MHz, CPU6:1199.988 MHz, CPU7:1199.988 MHz, 

       CCB:499.995 MHz,

       DDR:399.996 MHz (799.992 MT/s data rate) (Asynchronous), LBC:31.250 MHz

       FMAN0: 249.998 MHz

       FMAN1: 249.998 MHz

       PME:   249.998 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Board: P4080DS, Sys ID: 0x17, Sys Ver: 0x01, FPGA Ver: 0x03, vBank: 4 36-bit Addressing

I2C:   ready

DRAM:  Initializing....

Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN]  should not be set at the same time.

Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN]  should not be set at the same time.

6144M left unmapped

    DDR:  8 GB

""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""

It seams that it is something wrong with the DDR initiation.

Do I have a too old u-boot?

Do you think that a newer u-boot should work?

/Leif

 

 

 

 

  

Leif S?rman
Software Engineer
R&D OSE Labs Core
Enea
Skalholtsgatan 9,
Box 1033, SE-164 21 Kista, Sweden
Direct: +46 8 5071 4218
Mobile: +46 70 971 4218
leif.sorman at enea.com
www.enea.com 

 

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[U-Boot] 36-bit u-boot

[Andre Schwarz]

Leif,

> I have managed to flashed a 36-bits u-boot to my p4080 board.
>
> I have put in two 4Gb dimm into the board but it doesn't work.
>
> I got the following from u-boot.
>
>    
[snip]
> DRAM:  Initializing....
>
> Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN]  should not be set at the same time.
>    

"RD_EN" means "registered DIMM enable" which is read from PROM on memory 
module.

Looks like you have CONFIG_DDR_2T_TIMING defined in your board header 
... which is mutually exclusive with registered DIMM usage.
2T timing is only useful if you have AC timing violations regarding 
setup/hold on Addr/Cmd Bus.

> Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN]  should not be set at the same time.
>
> 6144M left unmapped
>
>      DDR:  8 GB
>
> """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
>
> It seams that it is something wrong with the DDR initiation.
>    

no.

You can either use unregistered DIMM modules or simply undefine 
CONFIG_DDR_2T_TIMING.


Cheers,
Andr?

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