From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Schwarz Date: Thu, 04 Nov 2010 15:49:06 +0100 Subject: [U-Boot] [PATCH] powerpc: do not fixup NULL ptrs In-Reply-To: References: <1287049904-18917-1-git-send-email-Joakim.Tjernlund@transmode.se> <1702240919.111.1287950899754.JavaMail.open-xchange@proteus> <20101024201832.DAF78134F26@gemini.denx.de> <739387466.116.1287952424329.JavaMail.open-xchange@proteus> <4CC58B1B.8040005@matrix-vision.de> <20101104095742.5C4AC12A81E3@gemini.denx.de> <025701cb7c0f$3b8c3870$b2a4a950$@pont@sdcsystems.com> <4CD2A3AD.6040605@matrix-vision.de> <4CD2A6EB.4060109@matrix-vision.de> Message-ID: <4CD2C7E2.1020907@matrix-vision.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Jocke, >> CPU: e300c4, MPC8379, Rev: 2.1 at 600 MHz, CSB: 400 MHz >> >> - Boot from NOR Flash >> - HRCW from I2C EEPROM >> - Reset Vector 0x100, i.e. low boot. >> > OK, almost the same as me, but I got a: > CPU: e300c2, MPC8321, Rev: 1.1 at 266.664 MHz, CSB: 133.332 MHz > > However, I think I just found the problem. > excellent ! > My tree is a bit messy now so no patch but it will be: > > Stick an isync (or sync) in > map_flash_by_law1 > .... > stw r4, LBLAWAR1(r3) /* LBLAWAR1<= 8MB Flash Size */ > isync //HERE !! HERE !! HERE > blr > ok - works for me, i.e. no quad-nop needed anymore. > I am guessing it takes a while for the stw r4, LBLAWAR1(r3) > to hit the HW so one must wait for it, not sure what is > best though, sync or isync? > If it is a timing issue why should have the nops influenced this ? I still wonder if this is the real problem and whether we might need more (i)syncs elsewhere ... > There is nothing wrong with my reset vector > > ok. Cheers, Andr? MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner