From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Schwarz Date: Thu, 04 Nov 2010 17:53:30 +0100 Subject: [U-Boot] [PATCH] powerpc: do not fixup NULL ptrs In-Reply-To: References: <1287049904-18917-1-git-send-email-Joakim.Tjernlund@transmode.se> <20101024201832.DAF78134F26@gemini.denx.de> <739387466.116.1287952424329.JavaMail.open-xchange@proteus> <4CC58B1B.8040005@matrix-vision.de> <20101104095742.5C4AC12A81E3@gemini.denx.de> <025701cb7c0f$3b8c3870$b2a4a950$@pont@sdcsystems.com> <4CD2A3AD.6040605@matrix-vision.de> <4CD2A6EB.4060109@matrix-vision.de> Message-ID: <4CD2E50A.9090407@matrix-vision.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Jocke, >> ok - works for me, i.e. no quad-nop needed anymore. >> > Does both your boards work now? > MPC8343 @ 400MHz never had any issues - it's still working with your patch applied. MPC8377 works fine up to 533MHz ... 600MHz+ still hangs. Looks like there are more sync missing. >>> I am guessing it takes a while for the stw r4, LBLAWAR1(r3) >>> to hit the HW so one must wait for it, not sure what is >>> best though, sync or isync? >>> >>> >> If it is a timing issue why should have the nops influenced this ? >> I still wonder if this is the real problem and whether we might need >> more (i)syncs elsewhere ... >> > You can try replacing the isync with 4 nops. That works > for me. moving the 4 nops after the blr doesn't work. > > I think it worked earlier by chance but the removal of > the flags changed timing, probably a cache line crossing > at the wrong place. > "works by chance" is probably not what we want. Anyway - good catch. Thanks again. Cheers, Andr? MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner