From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Schwarz Date: Fri, 05 Nov 2010 09:24:12 +0100 Subject: [U-Boot] [PATCH] mpc83xx: Make it boot again In-Reply-To: <63BE59A941660E44B1E66C95E0347C3C063666F3@az33exm25.fsl.freescale.net> References: <1288881912-4537-1-git-send-email-Joakim.Tjernlund@transmode.se> <63BE59A941660E44B1E66C95E0347C3C063666F1@az33exm25.fsl.freescale.net> <4CD2E5FD.3040109@freescale.com> <63BE59A941660E44B1E66C95E0347C3C063666F3@az33exm25.fsl.freescale.net> Message-ID: <4CD3BF2C.1070705@matrix-vision.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/04/2010 08:49 PM, Wood Scott-B07421 wrote: > > Timur Tabi wrote: > > Wood Scott-B07421 wrote: > > > To be totally safe, we probably want to do a readback plus twi (to > turn > > > a data dependency into a flow dependency) before the isync. > > > > twi == trap word immediate? > > Yes. > > > If so, I don't see how that will turn a data dependency into a flow > dependency. > > Is that some sort of side effect of twi? > > It decides based on the input register (data dependency) whether to > cause a trap (flow dependency). We never want it to actually trap, so > we set a condition that says never trap, but the dependency is still > there -- the hardware doesn't decode it as a no-op. > Might there be any other location this could be used for ? Actually my 8377 is running fine up to 533MHz core and csb up to 400MHz. As soon as core frequency rises to 600MHz+ there'll be frequent hangs during flush_dcache. core voltage is clean at 1.05V without any glitches or significant load steps. Can anybody confirm that current code runs stable on MPC837x at 600MHz+ ? Regards, Andr? MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner