From mboxrd@z Thu Jan 1 00:00:00 1970 From: Graeme Russ Date: Mon, 15 Nov 2010 06:34:37 +1100 Subject: [U-Boot] RFC: Aligning arch initialisation sequences In-Reply-To: <20101114192331.62ECA134F54@gemini.denx.de> References: <4CD67A22.9040802@gmail.com> <201011091835.38581.vapier@gentoo.org> <4CDE1107.80108@gmail.com> <4CDE4A53.4070106@free.fr> <4CDE741C.1020507@gmail.com> <4CDF6F2E.9040900@gmail.com> <4CDF7821.4080300@gmail.com> <4CDFA8E9.3050803@free.fr> <20101114103001.7EE2014EA7E@gemini.denx.de> <4CDFD1AE.1070409@free.fr> <20101114150102.DAAF914EA7E@gemini.denx.de> <4CE0221A.7030502@free.fr> <20101114192331.62ECA134F54@gemini.denx.de> Message-ID: <4CE039CD.90706@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 15/11/10 06:23, Wolfgang Denk wrote: > Dear Albert ARIBAUD, > > In message <4CE0221A.7030502@free.fr> you wrote: >> >> Alright, then I think we should document how we comply, or do not >> comply, with GNU EABI / AAPCS (maybe a README.arm that people could read >> up) -- and I think if there is a way to access GD both before and after >> relocation without making a register unavailable to the whole u-boot >> code, then we should use it. > > By the way - it should be not difficult to use a normal extern pointer > to reference the global data; see > "arch/powerpc/include/asm/global_data.h": > > 194 #if 1 > 195 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") > 196 #else /* We could use plain global data, but the resulting code is bigger */ > 197 #define XTRN_DECLARE_GLOBAL_DATA_PTR extern > 198 #define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ > 199 gd_t *gd > 200 #endif I think you will find this peculiar to PowerPC What you are talking about is exactly how x86 defines gd, but for x86, gd is not accessible until after relocation > > When I implemented this code I tested both versions. There is not > much of a difference, except that the register based version results > in smaller code. > Probably due to one less register load from memory for each gd access Regards, Graeme