[U-Boot] [PATCH 0/5] Add support for Freescale MX53

[U-Boot] [PATCH 0/5] Add support for Freescale MX53

[Jason Liu]

The following patch set add support for Freescale MX53

Jason Liu (5):
  MX5: Add initial support for MX53
  serial_mxc: add support for MX53 processor
  fec_mxc: add support for MX53 processor
  mxc_i2c: add support for MX53 processor
  MX5:MX53: add initial support for MX53EVK board

 MAINTAINERS                                 |    3 +
 arch/arm/cpu/armv7/mx5/iomux.c              |   30 ++-
 arch/arm/cpu/armv7/mx5/lowlevel_init.S      |   92 ++++---
 arch/arm/cpu/armv7/mx5/soc.c                |   14 +-
 arch/arm/cpu/armv7/u-boot.lds               |    1 +
 arch/arm/include/asm/arch-mx5/asm-offsets.h |    5 +
 arch/arm/include/asm/arch-mx5/imx-regs.h    |   78 ++---
 arch/arm/include/asm/arch-mx5/iomux.h       |  102 ------
 arch/arm/include/asm/arch-mx5/mx5x_pins.h   |  469 ++++++++++++++++++++++++++-
 board/freescale/mx53evk/Makefile            |   49 +++
 board/freescale/mx53evk/config.mk           |   23 ++
 board/freescale/mx53evk/ivt.S               |  289 +++++++++++++++++
 board/freescale/mx53evk/mx53evk.c           |  412 +++++++++++++++++++++++
 boards.cfg                                  |    1 +
 drivers/i2c/mxc_i2c.c                       |   18 +-
 drivers/net/fec_mxc.c                       |    2 +-
 drivers/net/fec_mxc.h                       |    4 +-
 drivers/serial/serial_mxc.c                 |    6 +
 include/configs/mx51evk.h                   |    3 +-
 include/configs/mx53evk.h                   |  213 ++++++++++++
 20 files changed, 1607 insertions(+), 207 deletions(-)
 mode change 100644 => 100755 arch/arm/cpu/armv7/mx5/iomux.c
 mode change 100644 => 100755 arch/arm/cpu/armv7/mx5/lowlevel_init.S
 mode change 100644 => 100755 arch/arm/include/asm/arch-mx5/imx-regs.h
 mode change 100644 => 100755 arch/arm/include/asm/arch-mx5/mx5x_pins.h
 create mode 100755 board/freescale/mx53evk/Makefile
 create mode 100755 board/freescale/mx53evk/config.mk
 create mode 100755 board/freescale/mx53evk/ivt.S
 create mode 100755 board/freescale/mx53evk/mx53evk.c
 mode change 100644 => 100755 drivers/i2c/mxc_i2c.c
 mode change 100644 => 100755 include/configs/mx51evk.h
 create mode 100755 include/configs/mx53evk.h

[U-Boot] [PATCH 1/5] MX5: Add initial support for MX53

[Jason Liu]

Add initial support for Freescale MX53 processor,

- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro

---
Changes for v2:
--address some comments of Stefano Babic,

Signed-off-by: Jason Liu <r64343@freescale.com>
---
 arch/arm/cpu/armv7/mx5/iomux.c              |   30 ++-
 arch/arm/cpu/armv7/mx5/lowlevel_init.S      |   92 ++++---
 arch/arm/cpu/armv7/mx5/soc.c                |   14 +-
 arch/arm/include/asm/arch-mx5/asm-offsets.h |    5 +
 arch/arm/include/asm/arch-mx5/imx-regs.h    |   78 ++---
 arch/arm/include/asm/arch-mx5/iomux.h       |  102 ------
 arch/arm/include/asm/arch-mx5/mx5x_pins.h   |  469 ++++++++++++++++++++++++++-
 include/configs/mx51evk.h                   |    3 +-
 8 files changed, 594 insertions(+), 199 deletions(-)
 mode change 100644 => 100755 arch/arm/cpu/armv7/mx5/iomux.c
 mode change 100644 => 100755 arch/arm/cpu/armv7/mx5/lowlevel_init.S
 mode change 100644 => 100755 arch/arm/include/asm/arch-mx5/imx-regs.h
 mode change 100644 => 100755 arch/arm/include/asm/arch-mx5/mx5x_pins.h
 mode change 100644 => 100755 include/configs/mx51evk.h

diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
old mode 100644
new mode 100755
index e8928d5..d4e3bbb
--- a/arch/arm/cpu/armv7/mx5/iomux.c
+++ b/arch/arm/cpu/armv7/mx5/iomux.c
@@ -34,7 +34,7 @@ enum iomux_reg_addr {
 	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
 	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
 	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
-	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
+	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
 };
 
 #define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
@@ -44,11 +44,12 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin)
 {
 	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
 
+#if defined(CONFIG_MX51)
 	if (is_soc_rev(CHIP_REV_2_0) < 0) {
 		/*
 		 * Fixup register address:
-		 *	i.MX51 TO1 has offset with the register
-		 * 	which is define as TO2.
+		 * i.MX51 TO1 has offset with the register
+		 * which is define as TO2.
 		 */
 		if ((pin == MX51_PIN_NANDF_RB5) ||
 			(pin == MX51_PIN_NANDF_RB6) ||
@@ -59,6 +60,7 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin)
 		else if (mux_reg >= 0x130)
 			mux_reg += 0xC;
 	}
+#endif
 	mux_reg += IOMUXSW_MUX_CTL;
 	return mux_reg;
 }
@@ -68,11 +70,12 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
 {
 	u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
 
+#if defined(CONFIG_MX51)
 	if (is_soc_rev(CHIP_REV_2_0) < 0) {
 		/*
 		 * Fixup register address:
-		 *	i.MX51 TO1 has offset with the register
-		 * 	which is define as TO2.
+		 * i.MX51 TO1 has offset with the register
+		 * which is define as TO2.
 		 */
 		if ((pin == MX51_PIN_NANDF_RB5) ||
 			(pin == MX51_PIN_NANDF_RB6) ||
@@ -91,6 +94,7 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
 		else
 			pad_reg += 8;
 	}
+#endif
 	pad_reg += IOMUXSW_PAD_CTL;
 	return pad_reg;
 }
@@ -98,10 +102,13 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
 /* Get the last iomux register address */
 static inline u32 get_mux_end(void)
 {
+#if defined(CONFIG_MX51)
 	if (is_soc_rev(CHIP_REV_2_0) < 0)
 		return IOMUXC_BASE_ADDR + (0x3F8 - 4);
 	else
 		return IOMUXC_BASE_ADDR + (0x3F0 - 4);
+#endif
+	return IOMUXSW_MUX_END;
 }
 
 /*
@@ -164,3 +171,16 @@ unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
 	u32 pad_reg = get_pad_reg(pin);
 	return readl(pad_reg);
 }
+
+/*
+ * This function configures daisy-chain
+ *
+ * @param input    index of input select register
+ * @param config   the binary value of elements
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+	u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+	writel(config, reg);
+}
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
old mode 100644
new mode 100755
index e984870..05372ca
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -70,6 +70,7 @@
 
 /* M4IF setup */
 .macro init_m4if
+#ifdef CONFIG_MX51
 	/* VPU and IPU given higher priority (0x4)
 	 * IPU accesses with ID=0x1 given highest priority (=0xA)
 	 */
@@ -87,27 +88,31 @@
 	ldr r1, =0x001901A3
 	str r1, [r0, #0x48]
 
+#endif
 .endm /* init_m4if */
 
 .macro setup_pll pll, freq
-	ldr r2, =\pll
+	ldr r0, =\pll
 	ldr r1, =0x00001232
-	str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 	mov r1, #0x2
-	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 
-	str r3, [r2, #PLL_DP_OP]
-	str r3, [r2, #PLL_DP_HFS_OP]
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
 
-	str r4, [r2, #PLL_DP_MFD]
-	str r4, [r2, #PLL_DP_HFS_MFD]
+	ldr r1,	W_DP_MFD_\freq
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
 
-	str r5, [r2, #PLL_DP_MFN]
-	str r5, [r2, #PLL_DP_HFS_MFN]
+	ldr r1,  W_DP_MFN_\freq
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
 
 	ldr r1, =0x00001232
-	str r1, [r2, #PLL_DP_CTL]
-1:	ldr r1, [r2, #PLL_DP_CTL]
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
 	ands r1, r1, #0x1
 	beq 1b
 .endm
@@ -115,6 +120,7 @@
 .macro init_clock
 	ldr r0, =CCM_BASE_ADDR
 
+#if defined(CONFIG_MX51)
 	/* Gate of clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
@@ -141,19 +147,16 @@
 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
 	cmp r1, #0x0
 	bne 1b
+#endif
 
 	/* Switch ARM to step clock */
 	mov r1, #0x4
 	str r1, [r0, #CLKCTL_CCSR]
-	mov r3, #DP_OP_800
-	mov r4, #DP_MFD_800
-	mov r5, #DP_MFN_800
-	setup_pll PLL1_BASE_ADDR
 
-	mov r3, #DP_OP_665
-	mov r4, #DP_MFD_665
-	mov r5, #DP_MFN_665
-	setup_pll PLL3_BASE_ADDR
+	setup_pll PLL1_BASE_ADDR, 800
+
+#if defined(CONFIG_MX51)
+	setup_pll PLL3_BASE_ADDR, 665
 
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
@@ -162,10 +165,7 @@
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]
-	mov r3, #DP_OP_665
-	mov r4, #DP_MFD_665
-	mov r5, #DP_MFN_665
-	setup_pll PLL2_BASE_ADDR
+	setup_pll PLL2_BASE_ADDR, 665
 
 	/* Switch peripheral to PLL2 */
 	ldr r0, =CCM_BASE_ADDR
@@ -174,12 +174,8 @@
 	ldr r1, =0x000020C0
 	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
-
-	mov r3, #DP_OP_216
-	mov r4, #DP_MFD_216
-	mov r5, #DP_MFN_216
-	setup_pll PLL3_BASE_ADDR
-
+#endif
+	setup_pll PLL3_BASE_ADDR, 216
 
 	/* Set the platform clock dividers */
 	ldr r0, =ARM_BASE_ADDR
@@ -188,18 +184,24 @@
 
 	ldr r0, =CCM_BASE_ADDR
 
+#if defined(CONFIG_MX51)
 	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
 	ldr r1, =0x0
 	ldr r3, [r1, #ROM_SI_REV]
 	cmp r3, #0x10
 	movls r1, #0x1
 	movhi r1, #0
-	str r1, [r0, #CLKCTL_CACRR]
+#else
+	/* Run@half speed, then full till we increase VDDGP */
+	mov r1, #1
 
+#endif
+	str r1, [r0, #CLKCTL_CACRR]
 	/* Switch ARM back to PLL 1 */
 	mov r1, #0
 	str r1, [r0, #CLKCTL_CCSR]
 
+#if defined(CONFIG_MX51)
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
 	ldr r1, =0x000020C2
@@ -208,6 +210,7 @@
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
 	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
 	str r1, [r0, #CLKCTL_CBCDR]
+#endif
 
 	/* Restore the default values in the Gate registers */
 	ldr r1, =0xFFFFFFFF
@@ -218,13 +221,23 @@
 	str r1, [r0, #CLKCTL_CCGR4]
 	str r1, [r0, #CLKCTL_CCGR5]
 	str r1, [r0, #CLKCTL_CCGR6]
+#if defined(CONFIG_MX53)
+	str r1, [r0, #CLKCTL_CCGR7]
+#endif
 
+#if defined(CONFIG_MX51)
 	/* Use PLL 2 for UART's, get 66.5MHz from it */
 	ldr r1, =0xA5A2A020
 	str r1, [r0, #CLKCTL_CSCMR1]
 	ldr r1, =0x00C30321
 	str r1, [r0, #CLKCTL_CSCDR1]
-
+#elif defined(CONFIG_MX53)
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	orr r1, r1, #0x3f
+	eor r1, r1, #0x3f
+	orr r1, r1, #0x21
+	str r1, [r0, #CLKCTL_CSCDR1]
+#endif
 	/* make sure divider effective */
 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
 	cmp r1, #0x0
@@ -249,6 +262,7 @@
 
 .globl lowlevel_init
 lowlevel_init:
+#if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #(1 << 23)
@@ -256,6 +270,7 @@ lowlevel_init:
 	ldr r1, [r0, #0x4]
 	orr r1, r1, #(1 << 23)
 	str r1, [r0, #0x4]
+#endif
 
 	init_l2cc
 
@@ -269,9 +284,12 @@ lowlevel_init:
 	mov pc,lr
 
 /* Board level setting value */
-DDR_PERCHARGE_CMD:	.word 0x04008008
-DDR_REFRESH_CMD:	.word 0x00008010
-DDR_LMR1_W:		.word 0x00338018
-DDR_LMR_CMD:		.word 0xB2220000
-DDR_TIMING_W:		.word 0xB02567A9
-DDR_MISC_W:		.word 0x000A0104
+W_DP_OP_800:              .word DP_OP_800
+W_DP_MFD_800:             .word DP_MFD_800
+W_DP_MFN_800:             .word DP_MFN_800
+W_DP_OP_665:              .word DP_OP_665
+W_DP_MFD_665:             .word DP_MFD_665
+W_DP_MFN_665:             .word DP_MFN_665
+W_DP_OP_216:              .word DP_OP_216
+W_DP_MFD_216:             .word DP_MFD_216
+W_DP_MFN_216:             .word DP_MFN_216
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 2900119..f5e0283 100644
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -35,6 +35,8 @@
 
 #if defined(CONFIG_MX51)
 #define CPU_TYPE 0x51000
+#elif defined(CONFIG_MX53)
+#define CPU_TYPE 0x53000
 #else
 #error "CPU_TYPE not defined"
 #endif
@@ -44,6 +46,7 @@ u32 get_cpu_rev(void)
 	int system_rev = CPU_TYPE;
 	int reg = __raw_readl(ROM_SI_REV);
 
+#if defined(CONFIG_MX51)
 	switch (reg) {
 	case 0x02:
 		system_rev |= CHIP_REV_1_1;
@@ -57,11 +60,20 @@ u32 get_cpu_rev(void)
 	case 0x20:
 		system_rev |= CHIP_REV_3_0;
 		break;
-	return system_rev;
 	default:
 		system_rev |= CHIP_REV_1_0;
 		break;
 	}
+#else
+	switch (reg) {
+	case 0x20:
+		system_rev |= CHIP_REV_2_0;
+		break;
+	default:
+		system_rev |= CHIP_REV_1_0;
+		break;
+	}
+#endif
 	return system_rev;
 }
 
diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h
index afd2728..2258f2f 100644
--- a/arch/arm/include/asm/arch-mx5/asm-offsets.h
+++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h
@@ -37,7 +37,12 @@
 #define CLKCTL_CCGR4            0x78
 #define CLKCTL_CCGR5            0x7C
 #define CLKCTL_CCGR6            0x80
+#if defined(CONFIG_MX53)
+#define CLKCTL_CCGR7            0x84
 #define CLKCTL_CMEOR            0x84
+#elif defined(CONFIG_MX51)
+#define CLKCTL_CMEOR            0x84
+#endif
 
 /* DPLL */
 #define PLL_DP_CTL	0x00
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
old mode 100644
new mode 100755
index b45026d..8be7f4b
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -20,38 +20,36 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
+#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
+#define __ASM_ARCH_MX5_IMX_REGS_H__
 
-/*
- * IRAM
- */
+#if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
-#define IRAM_SIZE		0x00020000	/* 128 KB */
-/*
- * Graphics Memory of GPU
- */
-#define GPU_BASE_ADDR		0x20000000
-#define GPU_CTRL_BASE_ADDR	0x30000000
 #define IPU_CTRL_BASE_ADDR	0x40000000
-/*
- * Debug
- */
-#define DEBUG_BASE_ADDR		0x60000000
-#define ETB_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR	(DEBUG_BASE_ADDR + 0x00008000)
+#define SPBA0_BASE_ADDR         0x70000000
+#define AIPS1_BASE_ADDR         0x73F00000
+#define AIPS2_BASE_ADDR         0x83F00000
+#define CSD0_BASE_ADDR          0x90000000
+#define CSD1_BASE_ADDR          0xA0000000
+#define NFC_BASE_ADDR_AXI       0xCFFF0000
+#elif defined(CONFIG_MX53)
+#define IPU_CTRL_BASE_ADDR      0x18000000
+#define SPBA0_BASE_ADDR         0x50000000
+#define AIPS1_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR         0x63F00000
+#define CSD0_BASE_ADDR          0x70000000
+#define CSD1_BASE_ADDR          0xB0000000
+#define NFC_BASE_ADDR_AXI       0xF7FF0000
+#define IRAM_BASE_ADDR          0xF8000000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
+#define IRAM_SIZE		0x00020000	/* 128 KB */
 
 /*
  * SPBA global module enabled #0
  */
-#define SPBA0_BASE_ADDR 	0x70000000
-
 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
 #define UART3_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x0000C000)
@@ -68,8 +66,6 @@
 /*
  * AIPS 1
  */
-#define AIPS1_BASE_ADDR 	0x73F00000
-
 #define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
 #define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
 #define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
@@ -91,11 +87,14 @@
 #define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
 #define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
 
+#if defined(CONFIG_MX53)
+#define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
+#endif
 /*
  * AIPS 2
  */
-#define AIPS2_BASE_ADDR	0x83F00000
-
 #define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
 #define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
 #define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
@@ -129,26 +128,7 @@
 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
 
-#define TZIC_BASE_ADDR		0x8FFFC000
-
 /*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR		0x90000000
-#define CSD1_BASE_ADDR		0xA0000000
-#define CS0_BASE_ADDR		0xB0000000
-#define CS1_BASE_ADDR		0xB8000000
-#define CS2_BASE_ADDR		0xC0000000
-#define CS3_BASE_ADDR		0xC8000000
-#define CS4_BASE_ADDR		0xCC000000
-#define CS5_BASE_ADDR		0xCE000000
-
-/*
- * NFC
- */
-#define NFC_BASE_ADDR_AXI	0xCFFF0000	/* NAND flash AXI */
-
-/*!
  * Number of GPIO port as defined in the IC Spec
  */
 #define GPIO_PORT_NUM		4
@@ -311,4 +291,4 @@ struct fuse_bank1_regs {
 
 #endif /* __ASSEMBLER__*/
 
-#endif				/*  __ASM_ARCH_MXC_MX51_H__ */
+#endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
index 0d91a24..760371b 100644
--- a/arch/arm/include/asm/arch-mx5/iomux.h
+++ b/arch/arm/include/asm/arch-mx5/iomux.h
@@ -70,108 +70,6 @@ typedef enum iomux_pad_config {
 	PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
 } iomux_pad_config_t;
 
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
-	MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
-	MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
-	MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
-	MUX_IN_FEC_FEC_COL_SELECT_INPUT,
-	MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
-	MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
-	MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
-	MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
-	MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
-	MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-
-	MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-
-	MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-
-	MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
-	MUX_INPUT_NUM_MUX,
-} iomux_input_select_t;
-
 /* various IOMUX input functions */
 typedef enum iomux_input_config {
 	INPUT_CTL_PATH0 = 0x0,
diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
old mode 100644
new mode 100755
index a564fce..a5cd773
--- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
@@ -86,12 +86,22 @@
 #define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
 #define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
 
-#define NON_MUX_I		PIN_TO_MUX_MASK
+#define NON_MUX_I              PIN_TO_MUX_MASK
+#define NON_PAD_I              PIN_TO_PAD_MASK
+
+#if defined(CONFIG_MX51)
 #define MUX_I_START		0x001C
 #define PAD_I_START		0x3F0
 #define INPUT_CTL_START		0x8C4
-#define INPUT_CTL_START_TO1	0x928
 #define MUX_I_END		(PAD_I_START - 4)
+#elif defined(CONFIG_MX53)
+#define MUX_I_START            0x0020
+#define PAD_I_START            0x348
+#define INPUT_CTL_START        0x730
+#define MUX_I_END              (PAD_I_START - 4)
+#else
+#error "CPU_TYPE not defined"
+#endif
 
 #define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
 	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
@@ -115,7 +125,7 @@
  * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
  * value is constructed based on the rules described above.
  */
-enum iomux_pins {
+enum {
 	MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
 	MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
 	MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
@@ -414,5 +424,458 @@ enum iomux_pins {
 	MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
 };
 
+enum {
+	MX53_PIN_GPIO_19  = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
+	MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
+	MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
+	MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
+	MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
+	MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
+	MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
+	MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
+	MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
+	MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
+	MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
+	MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
+	MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
+	MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
+	MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
+	MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
+	MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
+	MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
+	MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
+	MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
+	MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
+	MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
+	MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
+	MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
+	MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
+	MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
+	MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
+	MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
+	MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
+	MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
+	MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
+	MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
+	MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
+	MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
+	MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
+	MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
+	MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
+	MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
+	MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
+	MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
+	MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
+	MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
+	MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
+	MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
+	MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
+	MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
+	MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
+	MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
+	MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
+	MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
+	MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
+	MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
+	MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
+	MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
+	MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
+	MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
+	MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
+	MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
+	MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
+	MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
+	MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
+	MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
+	MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
+	MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
+	MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
+	MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
+	MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
+	MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
+	MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
+	MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
+	MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
+	MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
+	MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
+	MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
+	MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
+	MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
+	MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
+	MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
+	MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
+	MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
+	MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
+	MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
+	MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
+	MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
+	MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
+	MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
+	MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
+	MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
+	MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
+	MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
+	MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
+	MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
+	MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
+	MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
+	MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
+	MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
+	MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
+	MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
+	MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
+	MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
+	MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
+	MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
+	MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
+	MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
+	MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
+	MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
+	MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
+	MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
+	MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
+	MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
+	MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
+	MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
+	MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
+	MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
+	MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
+	MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
+	MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
+	MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
+	MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
+	MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
+	MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
+	MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
+	MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
+	MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
+	MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
+	MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
+	MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
+	MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
+	MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
+	MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
+	MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
+	MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
+	MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
+	MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
+	MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
+	MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
+	MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
+	MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
+	MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
+	MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
+	MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
+	MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
+	MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
+	MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
+	MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
+	MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
+	MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
+	MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
+	MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
+	MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
+	MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
+	MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
+	MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
+	MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
+	MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
+	MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
+	MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
+	MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
+	MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
+	MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
+	MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
+	MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
+	MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
+	MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
+	MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
+	MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
+	MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
+	MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
+	MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
+	MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
+	MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
+	MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
+	MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
+	MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
+	MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
+	MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
+	MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
+	MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
+	MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
+	MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
+	MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
+	MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
+	MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
+	MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
+	MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
+	MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
+	MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
+	MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
+	MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
+	MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
+	MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
+	MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
+	MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
+	MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
+	MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
+	MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
+	MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
+	MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
+	MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
+	MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
+	MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
+	MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
+	MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
+	MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
+	MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
+	MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
+	MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
+	MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
+	MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
+	MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
+	MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
+	MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
+	MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
+	MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
+	MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
+	MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
+	MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
+	MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
+	MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
+	MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
+	MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
+	MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
+	MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
+	MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
+	MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
+	MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
+	MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
+	MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
+	MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
+	MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
+	MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
+	MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
+	MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
+	MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
+	MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
+	MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
+	MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
+	MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
+	MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
+	MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
+	MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
+	MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
+	MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
+	MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
+	MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
+	MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
+	MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
+	MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
+	MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
+	MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
+	MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
+	MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
+	MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
+	MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
+	MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
+	MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
+	MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
+};
+/* various IOMUX input select register index */
+typedef enum iomux_input_select {
+	MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+	MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+	MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+	MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+	MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
+	/* TO2 */
+	MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
+	MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+	MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+	MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+	MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
+	MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+	MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+	MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+	MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+	MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
+	/* TO2 */
+	MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+	MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
+	MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
+	MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
+	MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
+	MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
+	MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
+	MX51_FEC_FEC_COL_SELECT_INPUT,
+	MX51_FEC_FEC_CRS_SELECT_INPUT,
+	MX51_FEC_FEC_MDI_SELECT_INPUT,
+	MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
+	MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
+	MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
+	MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
+	MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
+	MX51_FEC_FEC_RX_DV_SELECT_INPUT,
+	MX51_FEC_FEC_RX_ER_SELECT_INPUT,
+	MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
+	MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
+	/* TO2 */
+	MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
+	MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+	MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
+	/* TO2 */
+	MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
+	/* TO2 */
+	MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
+	MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
+	MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
+	MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
+	MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
+	MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
+	MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+	MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+	MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
+	MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
+	MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+	MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+	MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+	MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+	MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+	MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+	MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+	MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
+	MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
+	MX51PUT_NUM_MUX,
+	/* MX53 */
+	MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+	MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+	MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
+	MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
+	MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+	MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
+	MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
+	MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+	MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
+	MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+	MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,		/*0x760*/
+	MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
+	MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
+	MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
+	MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+	MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+	MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
+	MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
+	MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,	/*0x780*/
+	MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
+	MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+	MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+	MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+	MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+	MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
+	MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+	MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+	MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+	MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+	MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
+	MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,	/*0x7B0*/
+	MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
+	MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
+	MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
+	MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
+	MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+	MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,		/*0x7E0*/
+	MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
+	MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
+	MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
+	MX53_FEC_FEC_COL_SELECT_INPUT,	/*0x800*/
+	MX53_FEC_FEC_MDI_SELECT_INPUT,
+	MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
+	MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
+	MX53_GPC_PMIC_RDY_SELECT_INPUT,
+	MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+	MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+	MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+	MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+	MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
+	MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
+	MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+	MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+	MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+	MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
+	MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
+	MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,	/*0x840*/
+	MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
+	MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
+	MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+	MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+	MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+	MX53_MLB_MLBCLK_IN_SELECT_INPUT,
+	MX53_MLB_MLBDAT_IN_SELECT_INPUT,
+	MX53_MLB_MLBSIG_IN_SELECT_INPUT,
+	MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
+	MX53_SDMA_EVENTS_14_SELECT_INPUT,
+	MX53_SDMA_EVENTS_15_SELECT_INPUT,
+	MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,	/*0x870*/
+	MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+	MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+	MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+	MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
+	MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
+	MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
+	MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
+	MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
+} iomux_input_select_t;
+
 #endif				/* __ASSEMBLY__ */
 #endif				/* __ASM_ARCH_MX5_MX5X_PINS_H__ */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
old mode 100644
new mode 100755
index b4e5738..3d6d390
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -24,8 +24,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/arch/imx-regs.h>
-
  /* High Level Configuration Options */
 
 #define CONFIG_MX51	/* in a mx51 */
@@ -37,6 +35,7 @@
 
 #define CONFIG_L2_OFF
 
+#include <asm/arch/imx-regs.h>
 /*
  * Disabled for now due to build problems under Debian and a significant
  * increase in the final file size: 144260 vs. 109536 Bytes.
-- 
1.7.0.4

[U-Boot] [PATCH 1/5] MX5: Add initial support for MX53

[Wolfgang Denk]

Dear Jason Liu,

In message <1292494665-25674-2-git-send-email-r64343@freescale.com> you wrote:
> Add initial support for Freescale MX53 processor,
> 
> - Add the iomux support and the pin definition,
> - Add the regs definition, clean up some unused def from mx51,
> - Add the low level init support, make use the freq input of setup_pll macro
> 
> ---
> Changes for v2:
> --address some comments of Stefano Babic,

Damn. What are we supposed to make of that?

So you addresses some of his comments, but not all of them?

And what exactly did you change?  Or what did you not change?

Do you think we have time and resources to compare all your patch
versions?


Please provide a detailed explanation of changes for the whole patch
series!

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
How many Unix hacks does it take to change a light bulb?  Let's  see,
   can you use a shell script for that or does it need a C program?

[U-Boot] [PATCH 1/5] MX5: Add initial support for MX53

[Jason Liu]

Hi, Wolfgang,

2010/12/16 Wolfgang Denk <wd@denx.de>:
> Dear Jason Liu,
>
> In message <1292494665-25674-2-git-send-email-r64343@freescale.com> you wrote:
>> Add initial support for Freescale MX53 processor,
>>
>> - Add the iomux support and the pin definition,
>> - Add the regs definition, clean up some unused def from mx51,
>> - Add the low level init support, make use the freq input of setup_pll macro
>>
>> ---
>> Changes for v2:
>> --address some comments of Stefano Babic,
>
> Damn. What are we supposed to make of that?
>
> So you addresses some of his comments, but not all of them?
>
> And what exactly did you change? ?Or what did you not change?
>
> Do you think we have time and resources to compare all your patch
> versions?
>
>
> Please provide a detailed explanation of changes for the whole patch
> series!

U are right. I will take care later.

>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> How many Unix hacks does it take to change a light bulb? ?Let's ?see,
> ? can you use a shell script for that or does it need a C program?
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH 1/5] MX5: Add initial support for MX53

[Stefano Babic]

On 12/16/2010 11:17 AM, Jason Liu wrote:
> Add initial support for Freescale MX53 processor,
> 
> - Add the iomux support and the pin definition,
> - Add the regs definition, clean up some unused def from mx51,
> - Add the low level init support, make use the freq input of setup_pll macro
> 
> ---
> Changes for v2:
> --address some comments of Stefano Babic,

Please add always the version number in the e-mail subject, if it is a
resubmission, so we can know there is a previous version. Please add a
small list with all changes, as I cannot know which of them you implemented.

> diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
> index 2900119..f5e0283 100644
> --- a/arch/arm/cpu/armv7/mx5/soc.c
> +++ b/arch/arm/cpu/armv7/mx5/soc.c
> @@ -35,6 +35,8 @@
>  
>  #if defined(CONFIG_MX51)
>  #define CPU_TYPE 0x51000
> +#elif defined(CONFIG_MX53)
> +#define CPU_TYPE 0x53000
>  #else
>  #error "CPU_TYPE not defined"
>  #endif

In the previous discussion on first submit it seemd to me you agreed to
change this part, as we have already CONFIG_MX51 and CONFIG_MX53 and
additional defines are not needed. However, you resubmit the same code.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 1/5] MX5: Add initial support for MX53

[Jason Liu]

Hi, Stefano,

2010/12/16 Stefano Babic <sbabic@denx.de>:
> On 12/16/2010 11:17 AM, Jason Liu wrote:
>> Add initial support for Freescale MX53 processor,
>>
>> - Add the iomux support and the pin definition,
>> - Add the regs definition, clean up some unused def from mx51,
>> - Add the low level init support, make use the freq input of setup_pll macro
>>
>> ---
>> Changes for v2:
>> --address some comments of Stefano Babic,
>
> Please add always the version number in the e-mail subject, if it is a
> resubmission, so we can know there is a previous version. Please add a
> small list with all changes, as I cannot know which of them you implemented.

OK,  I will take care of it later.

>
>> diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
>> index 2900119..f5e0283 100644
>> --- a/arch/arm/cpu/armv7/mx5/soc.c
>> +++ b/arch/arm/cpu/armv7/mx5/soc.c
>> @@ -35,6 +35,8 @@
>>
>> ?#if defined(CONFIG_MX51)
>> ?#define CPU_TYPE 0x51000
>> +#elif defined(CONFIG_MX53)
>> +#define CPU_TYPE 0x53000
>> ?#else
>> ?#error "CPU_TYPE not defined"
>> ?#endif
>
> In the previous discussion on first submit it seemd to me you agreed to
> change this part, as we have already CONFIG_MX51 and CONFIG_MX53 and
> additional defines are not needed. However, you resubmit the same code.

This code is just adding MX53 based on MX51 code base. I don't think
there are some issues.
But if you insist on changing the original MX51 code and use another
way to do it, I will do it
in the coming patch set.

Thanks,

BR,
Jason

>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
> =====================================================================
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH 2/5] serial_mxc: add support for MX53 processor

[Jason Liu]

This patch add UART support for Freescale MX53 processor

Signed-off-by: Jason Liu <r64343@freescale.com>
---
 drivers/serial/serial_mxc.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index f96b21f..805f4c5 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -56,6 +56,12 @@
 #define UART_PHYS UART2_BASE_ADDR
 #elif defined(CONFIG_SYS_MX51_UART3)
 #define UART_PHYS UART3_BASE_ADDR
+#elif defined(CONFIG_SYS_MX53_UART1)
+#define UART_PHYS UART1_BASE_ADDR
+#elif defined(CONFIG_SYS_MX53_UART2)
+#define UART_PHYS UART2_BASE_ADDR
+#elif defined(CONFIG_SYS_MX53_UART3)
+#define UART_PHYS UART3_BASE_ADDR
 #else
 #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver"
 #endif
-- 
1.7.0.4

[U-Boot] [PATCH 3/5] fec_mxc: add support for MX53 processor

[Jason Liu]

This patch add FEC support for Freescale MX53 processor

Signed-off-by: Jason Liu <r64343@freescale.com>
---
 drivers/net/fec_mxc.c |    2 +-
 drivers/net/fec_mxc.h |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 0d0f392..652ced4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -354,7 +354,7 @@ static int fec_open(struct eth_device *edev)
 	 */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
 		&fec->eth->ecntrl);
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
 	udelay(100);
 	/*
 	 * setup the MII gasket for RMII mode
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 5d0d69d..1ba5161 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -147,7 +147,7 @@ struct ethernet_regs {
 
 	uint32_t res14[7];		/* MBAR_ETH + 0x2E4-2FC */
 
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
 	uint16_t miigsk_cfgr;		/* MBAR_ETH + 0x300 */
 	uint16_t res15[3];		/* MBAR_ETH + 0x302-306 */
 	uint16_t miigsk_enr;		/* MBAR_ETH + 0x308 */
@@ -204,7 +204,7 @@ struct ethernet_regs {
 #define FEC_ECNTRL_RESET		0x00000001	/* reset the FEC */
 #define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */
 
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
 /* defines for MIIGSK */
 /* RMII frequency control: 0=50MHz, 1=5MHz */
 #define MIIGSK_CFGR_FRCONT		(1 << 6)
-- 
1.7.0.4

[U-Boot] [PATCH 4/5] mxc_i2c: add support for MX53 processor

[Jason Liu]

This patch add I2C support for Freescale MX53 processor

Signed-off-by: Jason Liu <r64343@freescale.com>
---
 drivers/i2c/mxc_i2c.c |   18 +++++++++++++-----
 1 files changed, 13 insertions(+), 5 deletions(-)
 mode change 100644 => 100755 drivers/i2c/mxc_i2c.c

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
old mode 100644
new mode 100755
index 8e10fbb..f9f32cc
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -24,10 +24,11 @@
 
 #include <common.h>
 
-#if defined(CONFIG_HARD_I2C)
+#if defined(CONFIG_MX53)
+#include <asm/arch/clock.h>
+#endif
 
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#if defined(CONFIG_HARD_I2C)
 
 #define IADR	0x00
 #define IFDR	0x04
@@ -56,8 +57,10 @@
 #elif defined (CONFIG_SYS_I2C_MX31_PORT3)
 #define I2C_BASE	0x43f84000
 #define I2C_CLK_OFFSET	30
+#elif defined(CONFIG_SYS_I2C_PORT)
+#define I2C_BASE CONFIG_SYS_I2C_PORT
 #else
-#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver"
+#error "define CONFIG_SYS_I2C_PORT to use the I2C driver"
 #endif
 
 #ifdef DEBUG
@@ -72,11 +75,16 @@ static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
 
 void i2c_init(int speed, int unused)
 {
-	int freq = mx31_get_ipg_clk();
+	int freq;
 	int i;
 
+#ifdef CONFIG_MX31
+	freq = mx31_get_ipg_clk();
 	/* start the required I2C clock */
 	__REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET);
+#else
+	freq = mxc_get_clock(MXC_IPG_PERCLK);
+#endif
 
 	for (i = 0; i < 0x1f; i++)
 		if (freq / div[i] <= speed)
-- 
1.7.0.4

[U-Boot] [PATCH 4/5] mxc_i2c: add support for MX53 processor

[Heiko Schocher]

Hello Jason,

Jason Liu wrote:
> This patch add I2C support for Freescale MX53 processor
> 
> Signed-off-by: Jason Liu <r64343@freescale.com>
> ---
>  drivers/i2c/mxc_i2c.c |   18 +++++++++++++-----
>  1 files changed, 13 insertions(+), 5 deletions(-)
>  mode change 100644 => 100755 drivers/i2c/mxc_i2c.c
> 
> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
> old mode 100644
> new mode 100755
> index 8e10fbb..f9f32cc
> --- a/drivers/i2c/mxc_i2c.c
> +++ b/drivers/i2c/mxc_i2c.c
> @@ -24,10 +24,11 @@
>  
>  #include <common.h>
>  
> -#if defined(CONFIG_HARD_I2C)
> +#if defined(CONFIG_MX53)
> +#include <asm/arch/clock.h>
> +#endif
>  
> -#include <asm/arch/mx31.h>
> -#include <asm/arch/mx31-regs.h>

Why do you delete this includes? That will break mx31 boards.
Please add instead a

#if defined(CONFIG_MX31) around it

> +#if defined(CONFIG_HARD_I2C)

Why you move this define here?

>  #define IADR	0x00
>  #define IFDR	0x04
> @@ -56,8 +57,10 @@
>  #elif defined (CONFIG_SYS_I2C_MX31_PORT3)
>  #define I2C_BASE	0x43f84000
>  #define I2C_CLK_OFFSET	30
> +#elif defined(CONFIG_SYS_I2C_PORT)
> +#define I2C_BASE CONFIG_SYS_I2C_PORT
>  #else
> -#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver"
> +#error "define CONFIG_SYS_I2C_PORT to use the I2C driver"

This error message will be not correct on mx31 based boards,
as they have to define CONFIG_SYS_I2C_MX31_PORTx, please correct.

>  #endif
>  
>  #ifdef DEBUG
> @@ -72,11 +75,16 @@ static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
>  
>  void i2c_init(int speed, int unused)
>  {
> -	int freq = mx31_get_ipg_clk();
> +	int freq;
>  	int i;
>  
> +#ifdef CONFIG_MX31
> +	freq = mx31_get_ipg_clk();
>  	/* start the required I2C clock */
>  	__REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET);
> +#else
> +	freq = mxc_get_clock(MXC_IPG_PERCLK);
> +#endif
>  
>  	for (i = 0; i < 0x1f; i++)
>  		if (freq / div[i] <= speed)

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 4/5] mxc_i2c: add support for MX53 processor

[Jason Liu]

Hi, Heiko

2010/12/16 Heiko Schocher <hs@denx.de>:
> Hello Jason,
>
> Jason Liu wrote:
>> This patch add I2C support for Freescale MX53 processor
>>
>> Signed-off-by: Jason Liu <r64343@freescale.com>
>> ---
>> ?drivers/i2c/mxc_i2c.c | ? 18 +++++++++++++-----
>> ?1 files changed, 13 insertions(+), 5 deletions(-)
>> ?mode change 100644 => 100755 drivers/i2c/mxc_i2c.c
>>
>> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
>> old mode 100644
>> new mode 100755
>> index 8e10fbb..f9f32cc
>> --- a/drivers/i2c/mxc_i2c.c
>> +++ b/drivers/i2c/mxc_i2c.c
>> @@ -24,10 +24,11 @@
>>
>> ?#include <common.h>
>>
>> -#if defined(CONFIG_HARD_I2C)
>> +#if defined(CONFIG_MX53)
>> +#include <asm/arch/clock.h>
>> +#endif
>>
>> -#include <asm/arch/mx31.h>
>> -#include <asm/arch/mx31-regs.h>
>
> Why do you delete this includes? That will break mx31 boards.
> Please add instead a

As I think there is no need to include it? Am I wrong?
I see the only one board to use MXC_I2C is phycore, but it will build error,

board.c: In function '__dram_init_banksize':
board.c:233: error: 'CONFIG_SYS_SDRAM_BASE' undeclared (first use in
this function)
board.c:233: error: (Each undeclared identifier is reported only once
board.c:233: error: for each function it appears in.)
board.c: In function 'board_init_f':
board.c:279: error: 'CONFIG_SYS_INIT_SP_ADDR' undeclared (first use in
this function)
board.c:312: error: 'CONFIG_SYS_SDRAM_BASE' undeclared (first use in
this function)
make[1]: *** [board.o] Error 1
make[1]: Leaving directory
`/home/r64343/work_space/u-boot-upstream/u-boot/arch/arm/lib'
make: *** [arch/arm/lib/libarm.o] Error 2

>
> #if defined(CONFIG_MX31) around it
>
>> +#if defined(CONFIG_HARD_I2C)
>
> Why you move this define here?
>
>> ?#define IADR 0x00
>> ?#define IFDR 0x04
>> @@ -56,8 +57,10 @@
>> ?#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
>> ?#define I2C_BASE ? ? 0x43f84000
>> ?#define I2C_CLK_OFFSET ? ? ? 30
>> +#elif defined(CONFIG_SYS_I2C_PORT)
>> +#define I2C_BASE CONFIG_SYS_I2C_PORT
>> ?#else
>> -#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver"
>> +#error "define CONFIG_SYS_I2C_PORT to use the I2C driver"
>
> This error message will be not correct on mx31 based boards,
> as they have to define CONFIG_SYS_I2C_MX31_PORTx, please correct.
>
>> ?#endif
>>
>> ?#ifdef DEBUG
>> @@ -72,11 +75,16 @@ static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
>>
>> ?void i2c_init(int speed, int unused)
>> ?{
>> - ? ? int freq = mx31_get_ipg_clk();
>> + ? ? int freq;
>> ? ? ? int i;
>>
>> +#ifdef CONFIG_MX31
>> + ? ? freq = mx31_get_ipg_clk();
>> ? ? ? /* start the required I2C clock */
>> ? ? ? __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET);
>> +#else
>> + ? ? freq = mxc_get_clock(MXC_IPG_PERCLK);
>> +#endif
>>
>> ? ? ? for (i = 0; i < 0x1f; i++)
>> ? ? ? ? ? ? ? if (freq / div[i] <= speed)
>
> bye,
> Heiko
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Jason Liu]

Add initial support for MX53EVK board support.
FEC, SD/MMC, UART, I2C, have been support.

Signed-off-by: Jason Liu <r64343@freescale.com>
---
 MAINTAINERS                       |    3 +
 arch/arm/cpu/armv7/u-boot.lds     |    1 +
 board/freescale/mx53evk/Makefile  |   49 +++++
 board/freescale/mx53evk/config.mk |   23 ++
 board/freescale/mx53evk/ivt.S     |  289 ++++++++++++++++++++++++++
 board/freescale/mx53evk/mx53evk.c |  412 +++++++++++++++++++++++++++++++++++++
 boards.cfg                        |    1 +
 include/configs/mx53evk.h         |  213 +++++++++++++++++++
 8 files changed, 991 insertions(+), 0 deletions(-)
 create mode 100755 board/freescale/mx53evk/Makefile
 create mode 100755 board/freescale/mx53evk/config.mk
 create mode 100755 board/freescale/mx53evk/ivt.S
 create mode 100755 board/freescale/mx53evk/mx53evk.c
 create mode 100755 include/configs/mx53evk.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 0590ad9..c87ca56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1085,6 +1085,9 @@ Peter Meerwald <devel@bct-electronic.com>
 
 	bct-brettl2	BF536
 
+Jason Liu <r64343@freescale.com>
+
+	MX53evk         i.MX53
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index 5725c30..7b6ab66 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -34,6 +34,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text	:
 	{
+		*(.ivt)
 		arch/arm/cpu/armv7/start.o	(.text)
 		*(.text)
 	}
diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile
new file mode 100755
index 0000000..c6dc1cd
--- /dev/null
+++ b/board/freescale/mx53evk/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx53evk.o
+SOBJS	:= ivt.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx53evk/config.mk b/board/freescale/mx53evk/config.mk
new file mode 100755
index 0000000..2b21a08
--- /dev/null
+++ b/board/freescale/mx53evk/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0x77800000
diff --git a/board/freescale/mx53evk/ivt.S b/board/freescale/mx53evk/ivt.S
new file mode 100755
index 0000000..f7a176f
--- /dev/null
+++ b/board/freescale/mx53evk/ivt.S
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * .word with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.section ".ivt"
+
+ivt_header:         .word 0x402000D1    /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:    .word (0xF8006400 + (plugin_start - CONFIG_SYS_TEXT_BASE))
+reserv1:            .word 0x0
+dcd_ptr:            .word 0x0
+boot_data_ptr:      .word (0xF8006400 + (boot_data - CONFIG_SYS_TEXT_BASE))
+self_ptr:           .word (0xF8006400 + (ivt_header - CONFIG_SYS_TEXT_BASE))
+app_code_csf:       .word 0x0
+reserv2:            .word 0x0
+boot_data:          .word 0xF8006000
+image_len:          .word 2*1024
+plugin:             .word 0x1
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:        .word 0x402000D1    /*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v:   .word _start        /*Entry point for the bootloader */
+reserv3:            .word 0x0
+dcd2_ptr:           .word 0x0
+boot_data2_ptr:     .word boot_data2
+self_ptr2:          .word ivt2_header
+app_code_csf2:      .word 0x0
+reserv4:            .word 0x0
+boot_data2:         .word (CONFIG_SYS_TEXT_BASE - 0x400)
+image_len2:         .word (_end - CONFIG_SYS_TEXT_BASE)
+plugin2:            .word 0x0
+
+
+/* Here starts the plugin code */
+plugin_start:
+	/* Save the return address and the function arguments */
+	push {r0-r3, lr}
+
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+
+	cmp r1, #0x20
+
+	/* IOMUX Setup */
+	ldr r0, =0x53fa8500
+	moveq r1, #0x00180000
+	movne r1, #0x00380000
+	mov r2, #0x00380000
+	add r2, r2, #0x40
+	add r3, r1, #0x40
+	mov r4, #0x00200000
+
+	str r1, [r0, #0x54]
+	str r2, [r0, #0x58]
+	str r1, [r0, #0x60]
+	str r3, [r0, #0x64]
+	str r2, [r0, #0x68]
+
+	streq r1, [r0, #0x70]
+	strne r4, [r0, #0x70]
+	str r1, [r0, #0x74]
+	streq r1, [r0, #0x78]
+	strne r4, [r0, #0x78]
+	str r2, [r0, #0x7c]
+	str r3, [r0, #0x80]
+	str r1, [r0, #0x84]
+	str r1, [r0, #0x88]
+	str r2, [r0, #0x90]
+	str r1, [r0, #0x94]
+
+	ldr r0, =0x53fa86f0
+	str r1, [r0, #0x0]
+	mov r2, #0x00000200
+	str r2, [r0, #0x4]
+	mov r2, #0x00000000
+	str r2, [r0, #0xc]
+
+	ldr r0, =0x53fa8700
+	str r2, [r0, #0x14]
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+	str r1, [r0, #0x20]
+
+	moveq r2, #0x02000000
+	movne r2, #0x06000000
+
+	str r2, [r0, #0x24]
+	str r1, [r0, #0x28]
+	str r1, [r0, #0x2c]
+
+	/* Initialize DDR2 memory - Hynix H5PS2G83AFR */
+	ldr r0, =ESDCTL_BASE_ADDR
+
+	ldreq r1, =0x31333530
+	ldrne r1, =0x2b2f3031
+	str r1, [r0, #0x088]
+
+	ldreq r1, =0x4a474a44
+	ldrne r1, =0x40363333
+	str r1, [r0, #0x090]
+
+	/* add 3 logic unit of delay to sdclk  */
+	ldr r1, =0x00000f00
+	str r1, [r0, #0x098]
+
+	ldr r1, =0x00000800
+	str r1, [r0, #0x0F8]
+
+	ldreq r1, =0x02490241
+	ldrne r1, =0x01310132
+	str r1, [r0, #0x07c]
+
+	ldreq r1, =0x01710171
+	ldrne r1, =0x0133014b
+	str r1, [r0, #0x080]
+
+	/* Enable bank interleaving, RALAT = 0x4, DDR2_EN = 1 */
+	ldr r1, =0x00001710
+	str r1, [r0, #0x018]
+
+	ldr r1, =0xc4110000
+	str r1, [r0, #0x00]
+
+	ldr r1, =0x4d5122d2
+	str r1, [r0, #0x0C]
+
+	ldr r1, =0x92d18a22
+	str r1, [r0, #0x10]
+
+	ldr r1, =0x00c70092
+	str r1, [r0, #0x14]
+
+	ldr r1, =0x000026d2
+	str r1, [r0, #0x2C]
+
+	ldr r1, =0x009f000e
+	str r1, [r0, #0x30]
+
+	ldr r1, =0x12272000
+	str r1, [r0, #0x08]
+
+	ldr r1, =0x00030012
+	str r1, [r0, #0x04]
+
+	ldr r1, =0x04008010
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008032
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008033
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008031
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0b5280b0
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x04008010
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008020
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008020
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0a528030
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x03c68031
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00468031
+	str r1, [r0, #0x1C]
+
+	/* Even though Rev B does not have DDR on CSD1, keep these
+	 * mode register initialization sequences for future uses since
+	 * it does not hurt to keep them
+	 */
+	ldr r1, =0x04008018
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0000803a
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0000803b
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008039
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0b528138
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x04008018
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008028
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00008028
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x0a528038
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x03c68039
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00468039
+	str r1, [r0, #0x1C]
+
+	ldr r1, =0x00005800
+	str r1, [r0, #0x20]
+
+	ldr r1, =0x00033337
+	str r1, [r0, #0x58]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1C]
+
+	/*
+	 * The following is to fill in those arguments for this ROM function pu_
+	 * irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+	 *
+	 * This function is used to copy data from the storage media into DDR.
+	 *
+	 * start - Initial (possibly partial) image load address on entry. Final
+	 *             image load address on exit.
+	 * bytes - Initial (possibly partial) image size on entry. Final image
+	 *             size on exit.
+	 * boot_data - Initial @ref ivt Boot Data load address.
+	 */
+	adr r0, DDR_DEST_ADDR
+	adr r1, COPY_SIZE
+	adr r2, BOOT_DATA
+before_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* Different ROM address for TO 1.0 & TO 2.0 */
+	moveq r4, #0x1800
+	addeq r4, r4, #0x4d
+	beq 2f
+	mov r4, #0x400000
+	add r4, r4, #0x5000
+	add r4, r4, #0xc7
+
+2:      blx r4 /* This address might change in future ROM versions */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* To return to ROM from plugin, we need to fill in these argument.
+	 * Here is what need to do:
+	 * Need to construct the param for the function before return to ROM:
+	 * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+	 */
+	pop {r0-r3, lr}
+	ldr r4, DDR_DEST_ADDR
+	str r4, [r0]
+	ldr r4, COPY_SIZE
+	str r4, [r1]
+	mov r4, #0x400  /* Point to the second IVT table at offset 0x42C */
+	add r4, r4, #0x2C
+	str r4, [r2]
+	mov r0, #1
+
+	bx lr          /* return back to ROM code */
+
+DDR_DEST_ADDR:    .word   (CONFIG_SYS_TEXT_BASE - 0x400)
+COPY_SIZE:        .word   _end - CONFIG_SYS_TEXT_BASE
+BOOT_DATA:        .word   (CONFIG_SYS_TEXT_BASE - 0x400)
+                  .word   _end - CONFIG_SYS_TEXT_BASE
+                  .word   0
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
new file mode 100755
index 0000000..ff6bfb2
--- /dev/null
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	/* UART1 RXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+	/* UART1 TXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+#ifdef CONFIG_I2C_MXC
+static void setup_i2c(unsigned int module_base)
+{
+	switch (module_base) {
+	case I2C1_BASE_ADDR:
+		/* i2c1 SDA */
+		mxc_request_iomux(MX53_PIN_CSI0_D8,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		/* i2c1 SCL */
+		mxc_request_iomux(MX53_PIN_CSI0_D9,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		break;
+	case I2C2_BASE_ADDR:
+		/* i2c2 SDA */
+		mxc_request_iomux(MX53_PIN_KEY_ROW3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+
+		/* i2c2 SCL */
+		mxc_request_iomux(MX53_PIN_KEY_COL3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
+				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+
+		break;
+	default:
+		printf("Invalid I2C base: 0x%x\n", module_base);
+		break;
+	}
+}
+
+void power_init(void)
+{
+	unsigned char buf[4] = { 0 };
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	/* Set core voltage VDDGP to 1.05V for 800MHZ */
+	buf[0] = 0x45;
+	buf[1] = 0x4a;
+	buf[2] = 0x52;
+	if (i2c_write(0x8, 24, 1, buf, 3))
+		return;
+
+	/* Set DDR voltage VDDA to 1.25V */
+	buf[0] = 0;
+	buf[1] = 0;
+	buf[2] = 0x1a;
+	if (i2c_write(0x8, 26, 1, buf, 3))
+		return;
+
+	if (is_soc_rev(CHIP_REV_2_0) == 0) {
+		/* Set VCC to 1.3V for TO2 */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1C;
+		if (i2c_write(0x8, 25, 1, buf, 3))
+			return;
+
+		/* Set VDDA to 1.3V for TO2 */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1C;
+		if (i2c_write(0x8, 26, 1, buf, 3))
+			return;
+	}
+
+	/* need to delay 100 ms to allow power supplies to ramp-up */
+	udelay(100000);
+
+	/* Raise the core frequency to 800MHz */
+	writel(0x0, &mxc_ccm->cacrr);
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+	/* FEC RXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	 /* FEC TXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC CRS */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+	{MMC_SDHC3_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = readl(GPIO3_BASE_ADDR) & 0x2000;
+	else
+		*cd = readl(GPIO3_BASE_ADDR) & 0x800;
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA0,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA1,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA2,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA3,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_EIM_DA13,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			break;
+		case 1:
+			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_IORDY,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA8,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA9,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA10,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA11,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA0,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA1,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA2,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA3,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_EIM_DA11,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+int board_init(void)
+{
+	system_rev = get_cpu_rev();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_I2C_MXC
+	setup_i2c(CONFIG_SYS_I2C_PORT);
+	power_init();
+#endif
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: MX53EVK [");
+
+	switch (__REG(SRC_BASE_ADDR + 0x8)) {
+	case 0x0001:
+		printf("POR");
+		break;
+	case 0x0009:
+		printf("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		printf("WDOG");
+		break;
+	default:
+		printf("unknown");
+	}
+	printf("]\n");
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index dcd5a12..736e88e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -101,6 +101,7 @@ omap5912osk                  arm         arm926ejs   -                   ti
 edminiv2                     arm         arm926ejs   -                   LaCie          orion5x
 ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
 mx51evk                      arm         armv7       mx51evk             freescale      mx5
+mx53evk                      arm         armv7       mx53evk             freescale      mx5
 vision2                      arm         armv7       vision2             ttcontrol      mx5
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
new file mode 100755
index 0000000..d8b39ad
--- /dev/null
+++ b/include/configs/mx53evk.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+
+#define CONFIG_MX53
+
+#define CONFIG_SYS_MX5_HCLK	24000000
+#define CONFIG_SYS_MX5_CLK32		32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_L2_OFF
+
+#include <asm/arch/imx-regs.h>
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define BOARD_LATE_INIT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX53_UART1
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C          1
+#define CONFIG_HARD_I2C         1
+#define CONFIG_I2C_MXC          1
+#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C_SLAVE            0xfe
+/*
+ * MMC Configs
+ * */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_PRIME	"FEC0"
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"MX53EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif				/* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Albert ARIBAUD]

Le 16/12/2010 11:17, Jason Liu a ?crit :

> diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
> index 5725c30..7b6ab66 100644
> --- a/arch/arm/cpu/armv7/u-boot.lds
> +++ b/arch/arm/cpu/armv7/u-boot.lds
> @@ -34,6 +34,7 @@ SECTIONS
>   	. = ALIGN(4);
>   	.text	:
>   	{
> +		*(.ivt)

NAK. This IVT looks suspiciously like an IPL or header for some 
bootloader to me. It should not be part of u-boot, but should be built 
separately then glued to u-boot.bin like is done for NAND bootings. 
U-boot LDS files for ARM should always start with the reset and 
exception vectors, i.e. start.o.

>   		arch/arm/cpu/armv7/start.o	(.text)
>   		*(.text)
>   	}

> diff --git a/board/freescale/mx53evk/ivt.S b/board/freescale/mx53evk/ivt.S
> new file mode 100755
> index 0000000..f7a176f
> --- /dev/null
> +++ b/board/freescale/mx53evk/ivt.S
> @@ -0,0 +1,289 @@
> +/*
> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * .word with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include<config.h>
> +
> +.section ".ivt"
> +
> +ivt_header:         .word 0x402000D1    /* Tag=0xD1, Len=0x0020, Ver=0x40 */
> +app_code_jump_v:    .word (0xF8006400 + (plugin_start - CONFIG_SYS_TEXT_BASE))
> +reserv1:            .word 0x0
> +dcd_ptr:            .word 0x0
> +boot_data_ptr:      .word (0xF8006400 + (boot_data - CONFIG_SYS_TEXT_BASE))
> +self_ptr:           .word (0xF8006400 + (ivt_header - CONFIG_SYS_TEXT_BASE))
> +app_code_csf:       .word 0x0
> +reserv2:            .word 0x0
> +boot_data:          .word 0xF8006000
> +image_len:          .word 2*1024
> +plugin:             .word 0x1
> +
> +/* Second IVT to give entry point into the bootloader copied to DDR */
> +ivt2_header:        .word 0x402000D1    /*Tag=0xD1, Len=0x0020, Ver=0x40 */
> +app2_code_jump_v:   .word _start        /*Entry point for the bootloader */
> +reserv3:            .word 0x0
> +dcd2_ptr:           .word 0x0
> +boot_data2_ptr:     .word boot_data2
> +self_ptr2:          .word ivt2_header
> +app_code_csf2:      .word 0x0
> +reserv4:            .word 0x0
> +boot_data2:         .word (CONFIG_SYS_TEXT_BASE - 0x400)
> +image_len2:         .word (_end - CONFIG_SYS_TEXT_BASE)
> +plugin2:            .word 0x0
> +
> +
> +/* Here starts the plugin code */
> +plugin_start:
> +	/* Save the return address and the function arguments */

The entry point of u-boot should be the reset vector. Obviously this is 
not a reset vector, and looks more like a hook that some ROM code 
expects to call as a subroutine. In any case, it should not be the entry 
code of u-boot.

Please consider refactoring this into two different binaries as NAND 
boot does.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Wolfgang Denk]

Dear Albert ARIBAUD,

In message <4D09EE68.4000506@free.fr> you wrote:
> 
> > diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
> > index 5725c30..7b6ab66 100644
> > --- a/arch/arm/cpu/armv7/u-boot.lds
> > +++ b/arch/arm/cpu/armv7/u-boot.lds
> > @@ -34,6 +34,7 @@ SECTIONS
> >   	. = ALIGN(4);
> >   	.text	:
> >   	{
> > +		*(.ivt)
>
> NAK. This IVT looks suspiciously like an IPL or header for some
> bootloader to me. It should not be part of u-boot, but should be built
> separately then glued to u-boot.bin like is done for NAND bootings.

... or like the u-boot.kwb or u-boot.imx images we already build for
other architectures.

Actually this should probably be added to u-boot.imx support?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Anarchy may not be the best form of government, but it's better  than
no government at all.

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Stefano Babic]

On 12/16/2010 11:17 AM, Jason Liu wrote:
> Add initial support for MX53EVK board support.
> FEC, SD/MMC, UART, I2C, have been support.
> 
> diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
> index 5725c30..7b6ab66 100644
> --- a/arch/arm/cpu/armv7/u-boot.lds
> +++ b/arch/arm/cpu/armv7/u-boot.lds
> @@ -34,6 +34,7 @@ SECTIONS
>  	. = ALIGN(4);
>  	.text	:
>  	{
> +		*(.ivt)
>  		arch/arm/cpu/armv7/start.o	(.text)
>  		*(.text)
>  	}

We have already discussed this point, see my previous answer here:

	http://marc.info/?l=u-boot&m=127793013695282&w=2

The solution in u-boot is *not* to link statically the IMX header to the
u-boot.bin, but to generate a u-boot.imx image with a configuration
file. This solution is already provided for the i.MX51 processor (same
family), and you should go on this way, modifying tools/imximage.c for
your needs, if required. This solution was previously discussed and
accepted on the ML and it is compatible with other processors from
different manufactures (kirchwood, see also u-boot.kwb).

As already answered by Albert and Wolfgang, the header must not be part
of u-boot.bin.

> +SOBJS	:= ivt.o

This should be removed, and a imximage.cfg file should be written.

> +plugin_start:
> +	/* Save the return address and the function arguments */
> +	push {r0-r3, lr}
> +
> +	ldr r0, =ROM_SI_REV
> +	ldr r1, [r0]
> +
> +	cmp r1, #0x20
> +
> +	/* IOMUX Setup */
> +	ldr r0, =0x53fa8500
> +	moveq r1, #0x00180000
> +	movne r1, #0x00380000
> +	mov r2, #0x00380000
> +	add r2, r2, #0x40
> +	add r3, r1, #0x40
> +	mov r4, #0x00200000
> +
> +	str r1, [r0, #0x54]
> +	str r2, [r0, #0x58]
> +	str r1, [r0, #0x60]
> +	str r3, [r0, #0x64]
> +	str r2, [r0, #0x68]
> +
> +	streq r1, [r0, #0x70]
> +	strne r4, [r0, #0x70]
> +	str r1, [r0, #0x74]
> +	streq r1, [r0, #0x78]
> +	strne r4, [r0, #0x78]
> +	str r2, [r0, #0x7c]
> +	str r3, [r0, #0x80]
> +	str r1, [r0, #0x84]
> +	str r1, [r0, #0x88]
> +	str r2, [r0, #0x90]
> +	str r1, [r0, #0x94]
> +
> +	ldr r0, =0x53fa86f0
> +	str r1, [r0, #0x0]
> +	mov r2, #0x00000200
> +	str r2, [r0, #0x4]
> +	mov r2, #0x00000000
> +	str r2, [r0, #0xc]
> +
> +	ldr r0, =0x53fa8700
> +	str r2, [r0, #0x14]
> +	str r1, [r0, #0x18]
> +	str r1, [r0, #0x1c]
> +	str r1, [r0, #0x20]
> +
> +	moveq r2, #0x02000000
> +	movne r2, #0x06000000
> +
> +	str r2, [r0, #0x24]
> +	str r1, [r0, #0x28]
> +	str r1, [r0, #0x2c]
> +
> +	/* Initialize DDR2 memory - Hynix H5PS2G83AFR */
> +	ldr r0, =ESDCTL_BASE_ADDR
> +
> +	ldreq r1, =0x31333530
> +	ldrne r1, =0x2b2f3031
> +	str r1, [r0, #0x088]
> +
> +	ldreq r1, =0x4a474a44
> +	ldrne r1, =0x40363333
> +	str r1, [r0, #0x090]
> +
> +	/* add 3 logic unit of delay to sdclk  */
> +	ldr r1, =0x00000f00
> +	str r1, [r0, #0x098]
> +
> +	ldr r1, =0x00000800
> +	str r1, [r0, #0x0F8]
> +
> +	ldreq r1, =0x02490241
> +	ldrne r1, =0x01310132
> +	str r1, [r0, #0x07c]
> +
> +	ldreq r1, =0x01710171
> +	ldrne r1, =0x0133014b
> +	str r1, [r0, #0x080]
> +
> +	/* Enable bank interleaving, RALAT = 0x4, DDR2_EN = 1 */
> +	ldr r1, =0x00001710
> +	str r1, [r0, #0x018]
> +
> +	ldr r1, =0xc4110000
> +	str r1, [r0, #0x00]
> +
> +	ldr r1, =0x4d5122d2
> +	str r1, [r0, #0x0C]
> +
> +	ldr r1, =0x92d18a22
> +	str r1, [r0, #0x10]
> +
> +	ldr r1, =0x00c70092
> +	str r1, [r0, #0x14]
> +
> +	ldr r1, =0x000026d2
> +	str r1, [r0, #0x2C]
> +
> +	ldr r1, =0x009f000e
> +	str r1, [r0, #0x30]
> +
> +	ldr r1, =0x12272000
> +	str r1, [r0, #0x08]
> +
> +	ldr r1, =0x00030012
> +	str r1, [r0, #0x04]
> +
> +	ldr r1, =0x04008010
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008032
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008033
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008031
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x0b5280b0
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x04008010
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008020
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008020
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x0a528030
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x03c68031
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00468031
> +	str r1, [r0, #0x1C]
> +
> +	/* Even though Rev B does not have DDR on CSD1, keep these
> +	 * mode register initialization sequences for future uses since
> +	 * it does not hurt to keep them
> +	 */
> +	ldr r1, =0x04008018
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x0000803a
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x0000803b
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008039
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x0b528138
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x04008018
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008028
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00008028
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x0a528038
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x03c68039
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00468039
> +	str r1, [r0, #0x1C]
> +
> +	ldr r1, =0x00005800
> +	str r1, [r0, #0x20]
> +
> +	ldr r1, =0x00033337
> +	str r1, [r0, #0x58]
> +
> +	ldr r1, =0x00000000
> +	str r1, [r0, #0x1C]
> +

Why do we need to write these registers in assembly ? Why cannot we move
them into board_init or board_early_init_f ? And again, should these
values described better in imximage.cfg ?

> diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
> new file mode 100755
> index 0000000..ff6bfb2
> --- /dev/null
> +++ b/board/freescale/mx53evk/mx53evk.c
> @@ -0,0 +1,412 @@
> +/*
> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> + *
> + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.

It seems to me that you derived this file from mx51evk.c, but you copied
the header with copyrights from another (MX31, maybe) file.

> +#ifdef CONFIG_I2C_MXC
> +static void setup_i2c(unsigned int module_base)

I think it is better to enumerate the i2c controller as done in manual
as with the physical address. Anyway, I do not see yet any released
manual for this processor on Freescale's site, so I cannot be more precise.

> +void power_init(void)
> +{
> +	unsigned char buf[4] = { 0 };
> +	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
> +
> +	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> +
> +	/* Set core voltage VDDGP to 1.05V for 800MHZ */
> +	buf[0] = 0x45;
> +	buf[1] = 0x4a;
> +	buf[2] = 0x52;

Please remove all fixed constants in the file and replaced them with
named constants, defined in a header file. Check vision2.c as reference.
This board uses the MC13892 PMIC controller, and ./include/mc13892.h
contains all required defines.

> +	if (i2c_write(0x8, 24, 1, buf, 3))
> +		return;

Ditto. The same globally.

> +	if (is_soc_rev(CHIP_REV_2_0) == 0) {

Please add some comments describing why depending on the processor
revision we should to manage the pmic in a different way.

> +int board_mmc_getcd(u8 *cd, struct mmc *mmc)
> +{
> +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +
> +	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
> +		*cd = readl(GPIO3_BASE_ADDR) & 0x2000;

Please change this. There is mxc_get_gpio() and mxc_set_gpio() accessors.

> +int board_init(void)
> +{
> +	system_rev = get_cpu_rev();

I think we can get rid of system_rev. It is not used in this function
and you can call get_cpu_rev() directly in checkboard() when the value
is really needed.

> +#ifdef BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_I2C_MXC

Is it the board working if the pmic is not configured ? As I remember
from mx51evk, the network did not work if the PMIC via SPI was not
configured. If this is the case even for mx53evk, setting CONFIG_I2C_MXC
is a must, else a lot of thing cannot work. Then I would prefer to
remove these #ifdef and producing an error if it is not set at the
beginning of the file.

> +int checkboard(void)
> +{
> +	puts("Board: MX53EVK [");
> +
> +	switch (__REG(SRC_BASE_ADDR + 0x8)) {

Again, there is a "src" structure for i.MX51. If it is not correct for
i.MX53, you have to adapt it in imx-regs.h, but you cannot access
directly to registers. Please use always the correct structure or define
newer ones if they do not exist.

> +/*
> + * Disabled for now due to build problems under Debian and a significant
> + * increase in the final file size: 144260 vs. 109536 Bytes.
> + */

I see the same comment in mx51evk.h, but does it make sense ?

> +/*
> + * I2C Configs
> + */
> +#define CONFIG_CMD_I2C          1
> +#define CONFIG_HARD_I2C         1
> +#define CONFIG_I2C_MXC          1
> +#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR

As stated before: port means an enumeration value (0,1,..N), and it is
set to a physical address.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Jason Liu]

Hi, Stefano,

2010/12/16 Stefano Babic <sbabic@denx.de>:
> On 12/16/2010 11:17 AM, Jason Liu wrote:
>> Add initial support for MX53EVK board support.
>> FEC, SD/MMC, UART, I2C, have been support.
>>
>> diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
>> index 5725c30..7b6ab66 100644
>> --- a/arch/arm/cpu/armv7/u-boot.lds
>> +++ b/arch/arm/cpu/armv7/u-boot.lds
>> @@ -34,6 +34,7 @@ SECTIONS
>> ? ? ? . = ALIGN(4);
>> ? ? ? .text ? :
>> ? ? ? {
>> + ? ? ? ? ? ? *(.ivt)
>> ? ? ? ? ? ? ? arch/arm/cpu/armv7/start.o ? ? ?(.text)
>> ? ? ? ? ? ? ? *(.text)
>> ? ? ? }
>
> We have already discussed this point, see my previous answer here:
>
> ? ? ? ?http://marc.info/?l=u-boot&m=127793013695282&w=2
>
> The solution in u-boot is *not* to link statically the IMX header to the
> u-boot.bin, but to generate a u-boot.imx image with a configuration
> file. This solution is already provided for the i.MX51 processor (same
> family), and you should go on this way, modifying tools/imximage.c for
> your needs, if required. This solution was previously discussed and
> accepted on the ML and it is compatible with other processors from
> different manufactures (kirchwood, see also u-boot.kwb).
>
> As already answered by Albert and Wolfgang, the header must not be part
> of u-boot.bin.

There is pretty much different with I.MX51 ROM,  we will not use DCD
data file to config the
DDR script since ROM has the DCD size limitation and use the advance
feature of what we
called plug-in,  the plug-in code must be in the first 2K of MMC card
from 0x400 offset, that's
why we need put this code section before start.S. The plug-in code
will be called by boot ROM
to do DDR init first and copy u-boot to DDR and jump to _start  to run it.

I know that you add the .imx format support, that's is simple to add
one flash header which can be
calculated staticly and glue it to u-boot.bin but it's impossible for
plug-in feature support of ROM by
using the same way.

Does anyone of expert like you and Albert and Wolfgang tell me how to
do it? It's very important for FSL
coming many SOCs support, since we will use plug-in feature of boot ROM.

>> +SOBJS ? ? ? ?:= ivt.o
>
> This should be removed, and a imximage.cfg file should be written.
>
>> +plugin_start:
>> + ? ? /* Save the return address and the function arguments */
>> + ? ? push {r0-r3, lr}
>> +
>> + ? ? ldr r0, =ROM_SI_REV
>> + ? ? ldr r1, [r0]
>> +
>> + ? ? cmp r1, #0x20
>> +
>> + ? ? /* IOMUX Setup */
>> + ? ? ldr r0, =0x53fa8500
>> + ? ? moveq r1, #0x00180000
>> + ? ? movne r1, #0x00380000
>> + ? ? mov r2, #0x00380000
>> + ? ? add r2, r2, #0x40
>> + ? ? add r3, r1, #0x40
>> + ? ? mov r4, #0x00200000
>> +
>> + ? ? str r1, [r0, #0x54]
>> + ? ? str r2, [r0, #0x58]
>> + ? ? str r1, [r0, #0x60]
>> + ? ? str r3, [r0, #0x64]
>> + ? ? str r2, [r0, #0x68]
>> +
>> + ? ? streq r1, [r0, #0x70]
>> + ? ? strne r4, [r0, #0x70]
>> + ? ? str r1, [r0, #0x74]
>> + ? ? streq r1, [r0, #0x78]
>> + ? ? strne r4, [r0, #0x78]
>> + ? ? str r2, [r0, #0x7c]
>> + ? ? str r3, [r0, #0x80]
>> + ? ? str r1, [r0, #0x84]
>> + ? ? str r1, [r0, #0x88]
>> + ? ? str r2, [r0, #0x90]
>> + ? ? str r1, [r0, #0x94]
>> +
>> + ? ? ldr r0, =0x53fa86f0
>> + ? ? str r1, [r0, #0x0]
>> + ? ? mov r2, #0x00000200
>> + ? ? str r2, [r0, #0x4]
>> + ? ? mov r2, #0x00000000
>> + ? ? str r2, [r0, #0xc]
>> +
>> + ? ? ldr r0, =0x53fa8700
>> + ? ? str r2, [r0, #0x14]
>> + ? ? str r1, [r0, #0x18]
>> + ? ? str r1, [r0, #0x1c]
>> + ? ? str r1, [r0, #0x20]
>> +
>> + ? ? moveq r2, #0x02000000
>> + ? ? movne r2, #0x06000000
>> +
>> + ? ? str r2, [r0, #0x24]
>> + ? ? str r1, [r0, #0x28]
>> + ? ? str r1, [r0, #0x2c]
>> +
>> + ? ? /* Initialize DDR2 memory - Hynix H5PS2G83AFR */
>> + ? ? ldr r0, =ESDCTL_BASE_ADDR
>> +
>> + ? ? ldreq r1, =0x31333530
>> + ? ? ldrne r1, =0x2b2f3031
>> + ? ? str r1, [r0, #0x088]
>> +
>> + ? ? ldreq r1, =0x4a474a44
>> + ? ? ldrne r1, =0x40363333
>> + ? ? str r1, [r0, #0x090]
>> +
>> + ? ? /* add 3 logic unit of delay to sdclk ?*/
>> + ? ? ldr r1, =0x00000f00
>> + ? ? str r1, [r0, #0x098]
>> +
>> + ? ? ldr r1, =0x00000800
>> + ? ? str r1, [r0, #0x0F8]
>> +
>> + ? ? ldreq r1, =0x02490241
>> + ? ? ldrne r1, =0x01310132
>> + ? ? str r1, [r0, #0x07c]
>> +
>> + ? ? ldreq r1, =0x01710171
>> + ? ? ldrne r1, =0x0133014b
>> + ? ? str r1, [r0, #0x080]
>> +
>> + ? ? /* Enable bank interleaving, RALAT = 0x4, DDR2_EN = 1 */
>> + ? ? ldr r1, =0x00001710
>> + ? ? str r1, [r0, #0x018]
>> +
>> + ? ? ldr r1, =0xc4110000
>> + ? ? str r1, [r0, #0x00]
>> +
>> + ? ? ldr r1, =0x4d5122d2
>> + ? ? str r1, [r0, #0x0C]
>> +
>> + ? ? ldr r1, =0x92d18a22
>> + ? ? str r1, [r0, #0x10]
>> +
>> + ? ? ldr r1, =0x00c70092
>> + ? ? str r1, [r0, #0x14]
>> +
>> + ? ? ldr r1, =0x000026d2
>> + ? ? str r1, [r0, #0x2C]
>> +
>> + ? ? ldr r1, =0x009f000e
>> + ? ? str r1, [r0, #0x30]
>> +
>> + ? ? ldr r1, =0x12272000
>> + ? ? str r1, [r0, #0x08]
>> +
>> + ? ? ldr r1, =0x00030012
>> + ? ? str r1, [r0, #0x04]
>> +
>> + ? ? ldr r1, =0x04008010
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008032
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008033
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008031
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x0b5280b0
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x04008010
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008020
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008020
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x0a528030
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x03c68031
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00468031
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? /* Even though Rev B does not have DDR on CSD1, keep these
>> + ? ? ?* mode register initialization sequences for future uses since
>> + ? ? ?* it does not hurt to keep them
>> + ? ? ?*/
>> + ? ? ldr r1, =0x04008018
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x0000803a
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x0000803b
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008039
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x0b528138
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x04008018
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008028
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00008028
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x0a528038
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x03c68039
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00468039
>> + ? ? str r1, [r0, #0x1C]
>> +
>> + ? ? ldr r1, =0x00005800
>> + ? ? str r1, [r0, #0x20]
>> +
>> + ? ? ldr r1, =0x00033337
>> + ? ? str r1, [r0, #0x58]
>> +
>> + ? ? ldr r1, =0x00000000
>> + ? ? str r1, [r0, #0x1C]
>> +
>
> Why do we need to write these registers in assembly ? Why cannot we move
> them into board_init or board_early_init_f ? And again, should these
> values described better in imximage.cfg ?

Yes, we need write it in assembly. Please see the comments above.
We can't put it into board_init or board_early_init_f, because it does
DDR init.
It *must* run in IRAM which load by ROM first.

>
>> diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
>> new file mode 100755
>> index 0000000..ff6bfb2
>> --- /dev/null
>> +++ b/board/freescale/mx53evk/mx53evk.c
>> @@ -0,0 +1,412 @@
>> +/*
>> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
>> + *
>> + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>
> It seems to me that you derived this file from mx51evk.c, but you copied
> the header with copyrights from another (MX31, maybe) file.

The file from FSL uboot.

>
>> +#ifdef CONFIG_I2C_MXC
>> +static void setup_i2c(unsigned int module_base)
>
> I think it is better to enumerate the i2c controller as done in manual
> as with the physical address. Anyway, I do not see yet any released
> manual for this processor on Freescale's site, so I cannot be more precise.

I can't catch your mean. The function just do i2c iomux setup, anything wrong?

>
>> +void power_init(void)
>> +{
>> + ? ? unsigned char buf[4] = { 0 };
>> + ? ? struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
>> +
>> + ? ? i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
>> +
>> + ? ? /* Set core voltage VDDGP to 1.05V for 800MHZ */
>> + ? ? buf[0] = 0x45;
>> + ? ? buf[1] = 0x4a;
>> + ? ? buf[2] = 0x52;
>
> Please remove all fixed constants in the file and replaced them with
> named constants, defined in a header file. Check vision2.c as reference.
> This board uses the MC13892 PMIC controller, and ./include/mc13892.h
> contains all required defines.

OK,


>
>> + ? ? if (i2c_write(0x8, 24, 1, buf, 3))
>> + ? ? ? ? ? ? return;
>
> Ditto. The same globally.
>
>> + ? ? if (is_soc_rev(CHIP_REV_2_0) == 0) {
>
> Please add some comments describing why depending on the processor
> revision we should to manage the pmic in a different way.

OK,

>
>> +int board_mmc_getcd(u8 *cd, struct mmc *mmc)
>> +{
>> + ? ? struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
>> +
>> + ? ? if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
>> + ? ? ? ? ? ? *cd = readl(GPIO3_BASE_ADDR) & 0x2000;
>
> Please change this. There is mxc_get_gpio() and mxc_set_gpio() accessors.

OK,

>
>> +int board_init(void)
>> +{
>> + ? ? system_rev = get_cpu_rev();
>
> I think we can get rid of system_rev. It is not used in this function
> and you can call get_cpu_rev() directly in checkboard() when the value
> is really needed.

OK,  currently, it's not used.

>
>> +#ifdef BOARD_LATE_INIT
>> +int board_late_init(void)
>> +{
>> +#ifdef CONFIG_I2C_MXC
>
> Is it the board working if the pmic is not configured ? As I remember
> from mx51evk, the network did not work if the PMIC via SPI was not
> configured. If this is the case even for mx53evk, setting CONFIG_I2C_MXC
> is a must, else a lot of thing cannot work. Then I would prefer to
> remove these #ifdef and producing an error if it is not set at the
> beginning of the file.

No, this is not the case like MX53. The power of FEC is default on of
this board.
We need change power before we can run CPU at full speed.

>
>> +int checkboard(void)
>> +{
>> + ? ? puts("Board: MX53EVK [");
>> +
>> + ? ? switch (__REG(SRC_BASE_ADDR + 0x8)) {
>
> Again, there is a "src" structure for i.MX51. If it is not correct for
> i.MX53, you have to adapt it in imx-regs.h, but you cannot access
> directly to registers. Please use always the correct structure or define
> newer ones if they do not exist.

Yes, OK,

>
>> +/*
>> + * Disabled for now due to build problems under Debian and a significant
>> + * increase in the final file size: 144260 vs. 109536 Bytes.
>> + */
>
> I see the same comment in mx51evk.h, but does it make sense ?

No, I think. We need remove it from mx51 too.

>
>> +/*
>> + * I2C Configs
>> + */
>> +#define CONFIG_CMD_I2C ? ? ? ? ?1
>> +#define CONFIG_HARD_I2C ? ? ? ? 1
>> +#define CONFIG_I2C_MXC ? ? ? ? ?1
>> +#define CONFIG_SYS_I2C_PORT ? ? ? ? ? ? I2C2_BASE_ADDR
>
> As stated before: port means an enumeration value (0,1,..N), and it is
> set to a physical address.

Yes, I will fix it.

Thanks,

BR,
Jason

>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
> =====================================================================
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> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Wolfgang Denk]

Dear Jason Liu,

In message <AANLkTik9SB4EP2YLMeCa-TNb4c7Z-2CPphLtBqfx6J8B@mail.gmail.com> you wrote:
> 
> There is pretty much different with I.MX51 ROM,  we will not use DCD
> data file to config the
> DDR script since ROM has the DCD size limitation and use the advance
> feature of what we
> called plug-in,  the plug-in code must be in the first 2K of MMC card
> from 0x400 offset, that's
> why we need put this code section before start.S. The plug-in code
> will be called by boot ROM
> to do DDR init first and copy u-boot to DDR and jump to _start  to run it.

It seems you did not try to think what it would actually mean to
change your code as requested.

Actually nne of the above is reason that it must be done in your way.
All this can be acchieved in the way Stefano suggested as well.

> I know that you add the .imx format support, that's is simple to add
> one flash header which can be
> calculated staticly and glue it to u-boot.bin but it's impossible for
> plug-in feature support of ROM by
> using the same way.

Please explain why is should be impossible? I cannot follow that.

> Does anyone of expert like you and Albert and Wolfgang tell me how to
> do it? It's very important for FSL

Um.. this statement is not very friendly. Do you mean you consider
Stefano to be no expert?  He is the iMX custodian, and there is reason
for that.

> coming many SOCs support, since we will use plug-in feature of boot ROM.

You have received a clear NAK from three persons on that: from
Stefano (iMX custodian), Albert (ARM custodian), and me.

Is this not clear enough?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Don't have a battle of wits with an unarmed opponent.

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Albert ARIBAUD]

Le 17/12/2010 04:05, Jason Liu a ?crit :

> There is pretty much different with I.MX51 ROM,  we will not use DCD
> data file to config the
> DDR script since ROM has the DCD size limitation and use the advance
> feature of what we
> called plug-in,  the plug-in code must be in the first 2K of MMC card
> from 0x400 offset, that's
> why we need put this code section before start.S.

This implication is simply not true, as far as I can tell. You do need 
to have this "plug-in" (will you explain in the end what it is exactly?) 
in the first 2K of MMC; but that does not mean it has to be put in 
u-boot and u-boot stored at start of MMC. You could just as well put the 
"plug-in" alone in the first 2K and u-boot from the second 2K onward, 
for all I understand:

> The plug-in code
> will be called by boot ROM
> to do DDR init first and copy u-boot to DDR and jump to _start  to run it.

If it has to copy u-boot to DDR, then it should ne be part of u-boot.

> Does anyone of expert like you and Albert and Wolfgang tell me how to
> do it? It's very important for FSL
> coming many SOCs support, since we will use plug-in feature of boot ROM.

The first thing, I think, would be to get back to gathering your exact 
requirements, and only those, as per your SoC specs. From what you say 
of these, the requirements are not "have u-boot start in the first 2K of 
MMC with the "plug-in' coming first", but "have some routine in the 
first 2K of MMC, said routine assumed to do DDR init and payload copy"; 
and then, start from these reqs *only*.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Stefano Babic]

On 12/17/2010 04:05 AM, Jason Liu wrote:
> There is pretty much different with I.MX51 ROM,  we will not use DCD
> data file to config the
> DDR script since ROM has the DCD size limitation and use the advance
> feature of what we
> called plug-in,  the plug-in code must be in the first 2K of MMC card
> from 0x400 offset, that's
> why we need put this code section before start.S. The plug-in code
> will be called by boot ROM
> to do DDR init first and copy u-boot to DDR and jump to _start  to run it.

As I am not understanding what you mean as "plugin", it seems to me you
need some code able to set-up RAM and copy the u-boot code. This method
looks like very similar to other SoCs, where a first stage boot loader
is needed or when we boot from NAND.

I do not find any reasonable argument to follow the methods you are
proposing and to link statically this code to u-boot. In U-Boot we have
already two mechanisms for do this initial setup, one using special
images (with .kwb and .imx images when the RBL of the SoC is able to do
the whole job), the second one with a first stage bootloader as nand_spl
does and as Albert has already suggested.

> Does anyone of expert like you and Albert and Wolfgang tell me how to
> do it? It's very important for FSL
> coming many SOCs support, since we will use plug-in feature of boot ROM.

I am really not understanding if this "plugin" feature is really
different as what we have with other SoCs or when we boot from NAND on
other SOCs. As I can up now understand, it is similar to other
approaches we have support already and I do not see a reason to
implement a new one.

Is there some released Freescale's documentation to allow to me to
better understand what you are meaning ?

> Yes, we need write it in assembly. Please see the comments above.
> We can't put it into board_init or board_early_init_f, because it does
> DDR init.
> It *must* run in IRAM which load by ROM first.

Running in IRAM is not a sufficient reason to do in this way. If I am
not wrong, we could reach the same behavior on a i.MX51, too, if we set
the app_code_jump in the header to point to an IRAM address. Then even
the i.MX51 RBL should copy the code from storage to IRAM and then jump
to this address, isnt it ?

> I can't catch your mean. The function just do i2c iomux setup, anything wrong?

My concern is related to the fact that the controllers are normally
enumerated as "port numbers" and you make the selection based on the
base address, that could be confusing. I see an approach of the type:

static void setup_i2c(unsigned int port_number)
{

	switch (port_number) {
		0:
			.....
			break;
		1:

	.........
}


more intuitive to understand.

>>> +     /* Set core voltage VDDGP to 1.05V for 800MHZ */
>>> +     buf[0] = 0x45;
>>> +     buf[1] = 0x4a;
>>> +     buf[2] = 0x52;
>>
>> Please remove all fixed constants in the file and replaced them with
>> named constants, defined in a header file. Check vision2.c as reference.
>> This board uses the MC13892 PMIC controller, and ./include/mc13892.h
>> contains all required defines.
> 
> OK,

As further comment: there is already a pmic driver in u-boot
(fsl_pmic.c), that hides the underlying communication between processor
and pmic itself. At the moment, only spi is implemented. It is better to
expand the fsl_pmic code to support i2c, too, and to use the accessors
pmic_reg_read() and pmic_reg_write() to access to the pmic internal
registers in the board related code.

> No, this is not the case like MX53. The power of FEC is default on of
> this board.
> We need change power before we can run CPU at full speed.

Ok, understood.

>>> +#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
>>
>> As stated before: port means an enumeration value (0,1,..N), and it is
>> set to a physical address.
> 
> Yes, I will fix it.

This comment is related to the previous one for the setup_i2c()
function. Sorry if I was not clear enough. As you describe the define
CONFIG_SYS_I2C_PORT, this should be a port number (0,1,..N) and the
setup_i2() should accept as parameter this enumeration value, not a base
address.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Jason Liu]

Hi, Stefano,

2010/12/17 Stefano Babic <sbabic@denx.de>:
> On 12/17/2010 04:05 AM, Jason Liu wrote:
>> There is pretty much different with I.MX51 ROM, ?we will not use DCD
>> data file to config the
>> DDR script since ROM has the DCD size limitation and use the advance
>> feature of what we
>> called plug-in, ?the plug-in code must be in the first 2K of MMC card
>> from 0x400 offset, that's
>> why we need put this code section before start.S. The plug-in code
>> will be called by boot ROM
>> to do DDR init first and copy u-boot to DDR and jump to _start ?to run it.
>
> As I am not understanding what you mean as "plugin", it seems to me you
> need some code able to set-up RAM and copy the u-boot code. This method
> looks like very similar to other SoCs, where a first stage boot loader
> is needed or when we boot from NAND.

Forget about the case about boot From NAND, we are talking about boot
from SD/MMC card here.
Why I call it here"plug-in", it due to it use the plugin feature of ROM.

This section of code is for ROM to load and run, thus it should meet
the ROM boot structure requirement.
The plugin feature of ROM can give more flexibility and it can
overcome some shortcomings of DCD(used on mx51).

By using this plugin we can get around the following issues:
1.	DCD size limitation issue, plugin can be the size of OCRAM free space region.
2.	Safe environment to re-configure PLL1 (without impacting SDRAM) as
the plugin runs from OCRAM.


>
> I do not find any reasonable argument to follow the methods you are
> proposing and to link statically this code to u-boot. In U-Boot we have
> already two mechanisms for do this initial setup, one using special
> images (with .kwb and .imx images when the RBL of the SoC is able to do
> the whole job), the second one with a first stage bootloader as nand_spl
> does and as Albert has already suggested.

I don't know .kwb format, but know .imx format. Here the .imx use the
DCD table to do DDR init
but with plugin, it need run the binary code not the DCD configure
table. So, We need use assembly
code to run the DDR init script.

>
>> Does anyone of expert like you and Albert and Wolfgang tell me how to
>> do it? It's very important for FSL
>> coming many SOCs support, since we will use plug-in feature of boot ROM.
>
> I am really not understanding if this "plugin" feature is really
> different as what we have with other SoCs or when we boot from NAND on
> other SOCs. As I can up now understand, it is similar to other
> approaches we have support already and I do not see a reason to
> implement a new one.

Here, We can talking about SD/MMC boot. It's some different with NAND boot.
It's different with MX51 DCD approach.

>
> Is there some released Freescale's documentation to allow to me to
> better understand what you are meaning ?
>
>> Yes, we need write it in assembly. Please see the comments above.
>> We can't put it into board_init or board_early_init_f, because it does
>> DDR init.
>> It *must* run in IRAM which load by ROM first.
>
> Running in IRAM is not a sufficient reason to do in this way. If I am
> not wrong, we could reach the same behavior on a i.MX51, too, if we set
> the app_code_jump in the header to point to an IRAM address. Then even
> the i.MX51 RBL should copy the code from storage to IRAM and then jump
> to this address, isnt it ?

ROM will only load 2KB data from the beginning of SD/MMC card. The
first 1KB is not used, it means
that only 1KB data is used. We need put ivt table and ddr init
assembly code into this
1KB section. So, we can't put the assembly code into board_init or
board_early_init_f.

>
>> I can't catch your mean. The function just do i2c iomux setup, anything wrong?
>
> My concern is related to the fact that the controllers are normally
> enumerated as "port numbers" and you make the selection based on the
> base address, that could be confusing. I see an approach of the type:
>
> static void setup_i2c(unsigned int port_number)
> {
>
> ? ? ? ?switch (port_number) {
> ? ? ? ? ? ? ? ?0:
> ? ? ? ? ? ? ? ? ? ? ? ?.....
> ? ? ? ? ? ? ? ? ? ? ? ?break;
> ? ? ? ? ? ? ? ?1:
>
> ? ? ? ?.........
> }
>
>
> more intuitive to understand.

Yes, agree.


>
>>>> + ? ? /* Set core voltage VDDGP to 1.05V for 800MHZ */
>>>> + ? ? buf[0] = 0x45;
>>>> + ? ? buf[1] = 0x4a;
>>>> + ? ? buf[2] = 0x52;
>>>
>>> Please remove all fixed constants in the file and replaced them with
>>> named constants, defined in a header file. Check vision2.c as reference.
>>> This board uses the MC13892 PMIC controller, and ./include/mc13892.h
>>> contains all required defines.
>>
>> OK,
>
> As further comment: there is already a pmic driver in u-boot
> (fsl_pmic.c), that hides the underlying communication between processor
> and pmic itself. At the moment, only spi is implemented. It is better to
> expand the fsl_pmic code to support i2c, too, and to use the accessors
> pmic_reg_read() and pmic_reg_write() to access to the pmic internal
> registers in the board related code.

OK, I will check that code and see how hard to expand fsl_pmic to support i2c,
which depends on the code scalability.

>
>> No, this is not the case like MX53. The power of FEC is default on of
>> this board.
>> We need change power before we can run CPU at full speed.
>
> Ok, understood.
>
>>>> +#define CONFIG_SYS_I2C_PORT ? ? ? ? ? ? I2C2_BASE_ADDR
>>>
>>> As stated before: port means an enumeration value (0,1,..N), and it is
>>> set to a physical address.
>>
>> Yes, I will fix it.
>
> This comment is related to the previous one for the setup_i2c()
> function. Sorry if I was not clear enough. As you describe the define
> CONFIG_SYS_I2C_PORT, this should be a port number (0,1,..N) and the
> setup_i2() should accept as parameter this enumeration value, not a base
> address.

OK, I get it. Thanks,

>
> Best regards,
> Stefano Babic
>
>
> --
> =====================================================================
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
> =====================================================================
>

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[John Rigby]

On Sun, Dec 19, 2010 at 10:19 PM, Jason Liu <liu.h.jason@gmail.com> wrote:
> Hi, Stefano,
>
> 2010/12/17 Stefano Babic <sbabic@denx.de>:
>> On 12/17/2010 04:05 AM, Jason Liu wrote:
>>> There is pretty much different with I.MX51 ROM, ?we will not use DCD
>>> data file to config the
>>> DDR script since ROM has the DCD size limitation and use the advance
>>> feature of what we
>>> called plug-in, ?the plug-in code must be in the first 2K of MMC card
>>> from 0x400 offset, that's
>>> why we need put this code section before start.S. The plug-in code
>>> will be called by boot ROM
>>> to do DDR init first and copy u-boot to DDR and jump to _start ?to run it.
>>
>> As I am not understanding what you mean as "plugin", it seems to me you
>> need some code able to set-up RAM and copy the u-boot code. This method
>> looks like very similar to other SoCs, where a first stage boot loader
>> is needed or when we boot from NAND.
>
> Forget about the case about boot From NAND, we are talking about boot
> from SD/MMC card here.
> Why I call it here"plug-in", it due to it use the plugin feature of ROM.
>
> This section of code is for ROM to load and run, thus it should meet
> the ROM boot structure requirement.
> The plugin feature of ROM can give more flexibility and it can
> overcome some shortcomings of DCD(used on mx51).
>
> By using this plugin we can get around the following issues:
> 1. ? ? ?DCD size limitation issue, plugin can be the size of OCRAM free space region.
> 2. ? ? ?Safe environment to re-configure PLL1 (without impacting SDRAM) as
> the plugin runs from OCRAM.
>
>

Jason:
No one is arguing about the use the plugin feature.  The objection is
to how you are getting the plugin bits into the u-boot image.  You
should use a tool to prepend the plugins to the u-boot.bin file in a
similar way to how mkimage is used for i.mx51 and others.

Stefano:
I know Freescale has a binary to do this but I don't believe the
source is available.  The binary is included as a package in the
i.mx28 BSP as well as some sample plugins.

You can find your way to the i.mx28 page by googling
"site:freescale.com i.mx28 BSP" and following the top most hit.  You
have to register to download the BSP.

Once you download the BSP you will find a source archive called
L2.6.31_10.08.01_SDK_source.tar.gz.

The sample plugin package is in the archive in a file called
L2.6.31_10.08.01_SDK_source/pkgs/imx-bootlets-src-10.08.01.tar.gz.  I
guess bootlets are another name for plugins.

The binary utility for creating bootlets from elf files is called
elftosb-0.4.tar.bz2 in the same archive.  The utility appears to be a
typical over engineered c++ pile of stuff.  One would think that you
could accomplish the same thing with objdump, and a patch to mkimage.

Chapter 12 of the i.mx28 Technical Reference Manual describes this, I
have not seen a doc for i.mx53 yet and am just assuming that it is the
same as i.mx28.
http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf

br,

John

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Jason Liu]

Hi, Stefano, Wolfgang, Albert, John

2010/12/20 John Rigby <john.rigby@linaro.org>:
> On Sun, Dec 19, 2010 at 10:19 PM, Jason Liu <liu.h.jason@gmail.com> wrote:

> Jason:
> No one is arguing about the use the plugin feature. ?The objection is
> to how you are getting the plugin bits into the u-boot image. ?You
> should use a tool to prepend the plugins to the u-boot.bin file in a
> similar way to how mkimage is used for i.mx51 and others.

I will change back to follow i.mx51 imximage format. Patch has been sent out.

Thanks for your comments on this issue.

BR,
Jason

>
> br,
>
> John
>

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Stefano Babic]

On 12/20/2010 07:52 AM, John Rigby wrote:

> Jason:
> No one is arguing about the use the plugin feature.  The objection is
> to how you are getting the plugin bits into the u-boot image.  You
> should use a tool to prepend the plugins to the u-boot.bin file in a
> similar way to how mkimage is used for i.mx51 and others.

Exactly.

> 
> Stefano:
> I know Freescale has a binary to do this but I don't believe the
> source is available.  The binary is included as a package in the
> i.mx28 BSP as well as some sample plugins.

Thanks for hints !

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Albert ARIBAUD]

Hi Jason,

(cutting to essential parts of the discussion)

Le 20/12/2010 06:19, Jason Liu a ?crit :

> Forget about the case about boot From NAND, we are talking about boot
> from SD/MMC card here.

Which is exactly the same: usually the ROM code is just sophisticated 
enough to do a single, small, read from the lowest address and execute 
what was read. How this small piece of code is called varies, but 
basically it does a first-stage bootstrap and loads the next piece, 
usually a (more) full-fledged bootloader.

> Why I call it here"plug-in", it due to it use the plugin feature of ROM.
>
> This section of code is for ROM to load and run, thus it should meet
> the ROM boot structure requirement.
> The plugin feature of ROM can give more flexibility and it can
> overcome some shortcomings of DCD(used on mx51).
>
> By using this plugin we can get around the following issues:
> 1.	DCD size limitation issue, plugin can be the size of OCRAM free space region.
> 2.	Safe environment to re-configure PLL1 (without impacting SDRAM) as
> the plugin runs from OCRAM.

This is certainly good, although I'm not familiar enough with the mx 
series to appreciate the improvements. What I can appreciate, though, is 
that you're decribing a first-stage bootloader of sorts, and that 
nothing in your description forces this "plug-in" to be linked with 
u-boot, and even less, to be linked instead of u(boot's start code.

> I don't know .kwb format, but know .imx format. Here the .imx use the
> DCD table to do DDR init
> but with plugin, it need run the binary code not the DCD configure
> table. So, We need use assembly
> code to run the DDR init script.

Right! But you don't need to tack this code inside the u-boot binary.

> Here, We can talking about SD/MMC boot. It's some different with NAND
> boot.

Not really. for this "plug-in" boot, the ROM loads a small "plug-in" 
from some fixed location in SD/MMC and executes it, hoping that it'll 
contribute to some initializations and to loading the next payload. 
Ditto for NAND boot.

> It's different with MX51 DCD approach.

AIUI, for mx51 providing added inits and payload info are is done by a 
pure-data header; that is indeed different from NAND and SD/MMC boot 
where doing inits and putting payload in RAM are done by code. But your 
approach, from what I see, is not a third way; it seems to be a 
combination of both the data and code approaches.

> ROM will only load 2KB data from the beginning of SD/MMC card. The
> first 1KB is not used, it means
> that only 1KB data is used. We need put ivt table and ddr init
> assembly code into this
> 1KB section. So, we can't put the assembly code into board_init or
> board_early_init_f.

I don't get this. Why can you only use 1 KB of IRAM? If your plugin is 
supposed to setup DDR, how come it cannot fit in the IRAM which is the 
only place where it can go? When the plug-in feature was designed, 
surely people knew about that 1 KB constraint, right?

Please, check your requirements and actual hardware constraints and come 
back with a simpler design where first stage bootloader will not "bleed 
over" the payload.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Wolfgang Denk]

Dear Jason Liu,

In message <1292494665-25674-6-git-send-email-r64343@freescale.com> you wrote:
> Add initial support for MX53EVK board support.
> FEC, SD/MMC, UART, I2C, have been support.
> 
> Signed-off-by: Jason Liu <r64343@freescale.com>

The following is in addition to previously made comments:

> --- /dev/null
> +++ b/board/freescale/mx53evk/config.mk

Drop that file.

> +CONFIG_SYS_TEXT_BASE = 0x77800000

This goes to the board config file instead.


> +/* size in bytes reserved for initial data */
> +#define BOARD_LATE_INIT

Seems to be a bogus comment?

> +/*
> + * Hardware drivers
> + */

What exactly are "Hardware drivers" ?   

> +#define CONFIG_SYS_MEMTEST_START       0x70000000
> +#define CONFIG_SYS_MEMTEST_END         0x10000

Please say - has this ever been tested?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Put your Nose to the Grindstone!
                 -- Amalgamated Plastic Surgeons and Toolmakers, Ltd.

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Jason Liu]

Hi, Wolfgang,

2010/12/17 Wolfgang Denk <wd@denx.de>:
> Dear Jason Liu,
>
> In message <1292494665-25674-6-git-send-email-r64343@freescale.com> you wrote:
>> Add initial support for MX53EVK board support.
>> FEC, SD/MMC, UART, I2C, have been support.
>>
>> Signed-off-by: Jason Liu <r64343@freescale.com>
>
> The following is in addition to previously made comments:
>
>> --- /dev/null
>> +++ b/board/freescale/mx53evk/config.mk
>
> Drop that file.
>
>> +CONFIG_SYS_TEXT_BASE = 0x77800000
>
> This goes to the board config file instead.

A lot of board support has this file as following,

./board/freescale/m5373evb/config.mk
CONFIG_SYS_TEXT_BASE = 0xFF800000
./board/freescale/m547xevb/config.mk
CONFIG_SYS_TEXT_BASE = 0xffe00000
./board/freescale/m5275evb/config.mk
CONFIG_SYS_TEXT_BASE = 0xFFE00000
./board/freescale/m5282evb/config.mk
CONFIG_SYS_TEXT_BASE = 0xffe00000
./board/freescale/m5249evb/config.mk
CONFIG_SYS_TEXT_BASE = 0xFF800000
./board/freescale/m548xevb/config.mk
./board/freescale/mx31ads/config.mk
CONFIG_SYS_TEXT_BASE = 0xffe00000
./board/freescale/m5271evb/config.mk
CONFIG_SYS_TEXT_BASE = 0x87ec0000
CONFIG_SYS_TEXT_BASE = 0x87f00000
./board/freescale/mx31pdk/config.mk
CONFIG_SYS_TEXT_BASE = 0x97800000
./board/freescale/mx51evk/config.mk

Do you mean that all the new added boards support need drop config.mk
in the future?

>
>
>> +/* size in bytes reserved for initial data */
>> +#define BOARD_LATE_INIT
>
> Seems to be a bogus comment?

Yes, will remove it.


>
>> +/*
>> + * Hardware drivers
>> + */
>
> What exactly are "Hardware drivers" ?

Means uart driver, I will change it.

>
>> +#define CONFIG_SYS_MEMTEST_START ? ? ? 0x70000000
>> +#define CONFIG_SYS_MEMTEST_END ? ? ? ? 0x10000
>
> Please say - has this ever been tested?

Yes,  tested.

Thanks,

BR,
Jason

>
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Put your Nose to the Grindstone!
> ? ? ? ? ? ? ? ? -- Amalgamated Plastic Surgeons and Toolmakers, Ltd.
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH 5/5] MX5:MX53: add initial support for MX53EVK board

[Wolfgang Denk]

Dear Jason Liu,

In message <AANLkTimTG7h_y5f8JwxG0QtMUEotRt73HLzsp8BMHciA@mail.gmail.com> you wrote:
> 
> A lot of board support has this file as following,
> 
> ./board/freescale/m5373evb/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0xFF800000
> ./board/freescale/m547xevb/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0xffe00000
> ./board/freescale/m5275evb/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0xFFE00000
> ./board/freescale/m5282evb/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0xffe00000
> ./board/freescale/m5249evb/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0xFF800000
> ./board/freescale/m548xevb/config.mk
> ./board/freescale/mx31ads/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0xffe00000
> ./board/freescale/m5271evb/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0x87ec0000
> CONFIG_SYS_TEXT_BASE =3D 0x87f00000
> ./board/freescale/mx31pdk/config.mk
> CONFIG_SYS_TEXT_BASE =3D 0x97800000
> ./board/freescale/mx51evk/config.mk

Yes, these all need to be cleaned up.  Patches welcome.

> Do you mean that all the new added boards support need drop config.mk
> in the future?

Yes.  At least to the extend possible - we want to concentrate all
configuration information in a single location (the board config file)
and not scatter it around over several places like Makefiles and
config.mk

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
An age is called Dark not because  the  light  fails  to  shine,  but
because people refuse to see it.           -- James Michener, "Space"

[U-Boot] [PATCH 0/5] Add support for Freescale MX53

[Wolfgang Denk]

Dear Jason Liu,

In message <1292494665-25674-1-git-send-email-r64343@freescale.com> you wrote:
> The following patch set add support for Freescale MX53
> 
> Jason Liu (5):
>   MX5: Add initial support for MX53
>   serial_mxc: add support for MX53 processor
>   fec_mxc: add support for MX53 processor
>   mxc_i2c: add support for MX53 processor
>   MX5:MX53: add initial support for MX53EVK board

Why do you not indictae in the Subject that this is a resubmission?
See
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Witch!  Witch!  They'll burn ya!
	-- Hag, "Tomorrow is Yesterday", stardate unknown