* [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support
@ 2010-12-29 12:38 Jason Liu
2010-12-29 12:38 ` [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor Jason Liu
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw)
To: u-boot
This patch add I2C interface for fsl_pmic driver support
Signed-off-by: Jason Liu <r64343@freescale.com>
---
Changes for v2:
- Address the comments from Stefano,
- factor out the param_check in pmic_reg for both spi/i2c
---
drivers/misc/fsl_pmic.c | 52 ++++++++++++++++++++++++++++++++++++++++++----
1 files changed, 47 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c
index 5ee1de1..b58854d 100644
--- a/drivers/misc/fsl_pmic.c
+++ b/drivers/misc/fsl_pmic.c
@@ -22,11 +22,55 @@
#include <config.h>
#include <common.h>
-#include <spi.h>
#include <asm/errno.h>
#include <linux/types.h>
#include <fsl_pmic.h>
+static int check_param(u32 reg, u32 write)
+{
+ if (reg > 63 || write > 1) {
+ printf("<reg num> = %d is invalid. Should be less then 63\n",
+ reg);
+ return -1;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_PMIC_I2C
+#include <i2c.h>
+static int init_done;
+
+u32 pmic_reg(u32 reg, u32 val, u32 write)
+{
+ unsigned char buf[4] = { 0 };
+ u32 ret_val = 0;
+
+ if (check_param(reg, write))
+ return -1;
+
+ if (init_done == 0) {
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ init_done = 1;
+ }
+
+ if (write) {
+ buf[0] = (val >> 16) & 0xff;
+ buf[1] = (val >> 8) & 0xff;
+ buf[2] = (val) & 0xff;
+ if (i2c_write(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3))
+ return -1;
+ } else {
+ if (i2c_read(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3)) {
+ return -1;
+ ret_val = buf[0] << 16 | buf[1] << 8 | buf[2];
+ }
+ }
+
+ return ret_val;
+}
+#else /* SPI interface */
+#include <spi.h>
static struct spi_slave *slave;
struct spi_slave *pmic_spi_probe(void)
@@ -55,11 +99,8 @@ u32 pmic_reg(u32 reg, u32 val, u32 write)
return -1;
}
- if (reg > 63 || write > 1) {
- printf("<reg num> = %d is invalid. Should be less then 63\n",
- reg);
+ if (check_param(reg, write))
return -1;
- }
if (spi_claim_bus(slave))
return -1;
@@ -87,6 +128,7 @@ u32 pmic_reg(u32 reg, u32 val, u32 write)
spi_release_bus(slave);
return cpu_to_be32(pmic_rx);
}
+#endif
void pmic_reg_write(u32 reg, u32 value)
{
--
1.7.0.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-30 12:09 ` Stefano Babic 2010-12-29 12:38 ` [U-Boot] [PATCH v3 2/8] fec_mxc: add " Jason Liu ` (7 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro --- Changes for v2: -address some comments of Stefano Babic, remove the is_soc_type and use #ifdef, -address the comments of stefano, remove CPU_TYPE def, remove something like /*0x760*/ comments in mx5x_pins.h. -fix the build break for vision2 board Signed-off-by: Jason Liu <r64343@freescale.com> --- arch/arm/cpu/armv7/mx5/iomux.c | 30 ++- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 91 +++--- arch/arm/cpu/armv7/mx5/soc.c | 22 +- arch/arm/include/asm/arch-mx5/asm-offsets.h | 5 + arch/arm/include/asm/arch-mx5/imx-regs.h | 78 ++--- arch/arm/include/asm/arch-mx5/iomux.h | 102 ------ arch/arm/include/asm/arch-mx5/mx5x_pins.h | 469 ++++++++++++++++++++++++++- include/configs/mx51evk.h | 3 +- include/configs/vision2.h | 3 +- 9 files changed, 599 insertions(+), 204 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c old mode 100644 new mode 100755 index e8928d5..d4e3bbb --- a/arch/arm/cpu/armv7/mx5/iomux.c +++ b/arch/arm/cpu/armv7/mx5/iomux.c @@ -34,7 +34,7 @@ enum iomux_reg_addr { IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, - IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR, + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START, }; #define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1) @@ -44,11 +44,12 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin) { u32 mux_reg = PIN_TO_IOMUX_MUX(pin); +#if defined(CONFIG_MX51) if (is_soc_rev(CHIP_REV_2_0) < 0) { /* * Fixup register address: - * i.MX51 TO1 has offset with the register - * which is define as TO2. + * i.MX51 TO1 has offset with the register + * which is define as TO2. */ if ((pin == MX51_PIN_NANDF_RB5) || (pin == MX51_PIN_NANDF_RB6) || @@ -59,6 +60,7 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin) else if (mux_reg >= 0x130) mux_reg += 0xC; } +#endif mux_reg += IOMUXSW_MUX_CTL; return mux_reg; } @@ -68,11 +70,12 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin) { u32 pad_reg = PIN_TO_IOMUX_PAD(pin); +#if defined(CONFIG_MX51) if (is_soc_rev(CHIP_REV_2_0) < 0) { /* * Fixup register address: - * i.MX51 TO1 has offset with the register - * which is define as TO2. + * i.MX51 TO1 has offset with the register + * which is define as TO2. */ if ((pin == MX51_PIN_NANDF_RB5) || (pin == MX51_PIN_NANDF_RB6) || @@ -91,6 +94,7 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin) else pad_reg += 8; } +#endif pad_reg += IOMUXSW_PAD_CTL; return pad_reg; } @@ -98,10 +102,13 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin) /* Get the last iomux register address */ static inline u32 get_mux_end(void) { +#if defined(CONFIG_MX51) if (is_soc_rev(CHIP_REV_2_0) < 0) return IOMUXC_BASE_ADDR + (0x3F8 - 4); else return IOMUXC_BASE_ADDR + (0x3F0 - 4); +#endif + return IOMUXSW_MUX_END; } /* @@ -164,3 +171,16 @@ unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) u32 pad_reg = get_pad_reg(pin); return readl(pad_reg); } + +/* + * This function configures daisy-chain + * + * @param input index of input select register + * @param config the binary value of elements + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + writel(config, reg); +} diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S old mode 100644 new mode 100755 index e984870..96ebfe2 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -70,6 +70,7 @@ /* M4IF setup */ .macro init_m4if +#ifdef CONFIG_MX51 /* VPU and IPU given higher priority (0x4) * IPU accesses with ID=0x1 given highest priority (=0xA) */ @@ -87,27 +88,31 @@ ldr r1, =0x001901A3 str r1, [r0, #0x48] +#endif .endm /* init_m4if */ .macro setup_pll pll, freq - ldr r2, =\pll + ldr r0, =\pll ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ mov r1, #0x2 - str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ - str r3, [r2, #PLL_DP_OP] - str r3, [r2, #PLL_DP_HFS_OP] + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] - str r4, [r2, #PLL_DP_MFD] - str r4, [r2, #PLL_DP_HFS_MFD] + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] - str r5, [r2, #PLL_DP_MFN] - str r5, [r2, #PLL_DP_HFS_MFN] + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] -1: ldr r1, [r2, #PLL_DP_CTL] + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 beq 1b .endm @@ -115,6 +120,7 @@ .macro init_clock ldr r0, =CCM_BASE_ADDR +#if defined(CONFIG_MX51) /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] @@ -141,19 +147,16 @@ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b +#endif /* Switch ARM to step clock */ mov r1, #0x4 str r1, [r0, #CLKCTL_CCSR] - mov r3, #DP_OP_800 - mov r4, #DP_MFD_800 - mov r5, #DP_MFN_800 - setup_pll PLL1_BASE_ADDR - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL3_BASE_ADDR + setup_pll PLL1_BASE_ADDR, 800 + +#if defined(CONFIG_MX51) + setup_pll PLL3_BASE_ADDR, 665 /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR @@ -162,10 +165,7 @@ str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL2_BASE_ADDR + setup_pll PLL2_BASE_ADDR, 665 /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR @@ -174,12 +174,8 @@ ldr r1, =0x000020C0 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] - - mov r3, #DP_OP_216 - mov r4, #DP_MFD_216 - mov r5, #DP_MFN_216 - setup_pll PLL3_BASE_ADDR - +#endif + setup_pll PLL3_BASE_ADDR, 216 /* Set the platform clock dividers */ ldr r0, =ARM_BASE_ADDR @@ -188,18 +184,23 @@ ldr r0, =CCM_BASE_ADDR +#if defined(CONFIG_MX51) /* Run 3.0@Full speed, for other TO's wait till we increase VDDGP */ ldr r1, =0x0 ldr r3, [r1, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0 - str r1, [r0, #CLKCTL_CACRR] +#else + mov r1, #0 +#endif + str r1, [r0, #CLKCTL_CACRR] /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR] +#if defined(CONFIG_MX51) /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ ldr r1, =0x000020C2 @@ -208,6 +209,7 @@ /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CONFIG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] +#endif /* Restore the default values in the Gate registers */ ldr r1, =0xFFFFFFFF @@ -218,13 +220,23 @@ str r1, [r0, #CLKCTL_CCGR4] str r1, [r0, #CLKCTL_CCGR5] str r1, [r0, #CLKCTL_CCGR6] +#if defined(CONFIG_MX53) + str r1, [r0, #CLKCTL_CCGR7] +#endif +#if defined(CONFIG_MX51) /* Use PLL 2 for UART's, get 66.5MHz from it */ ldr r1, =0xA5A2A020 str r1, [r0, #CLKCTL_CSCMR1] ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] - +#elif defined(CONFIG_MX53) + ldr r1, [r0, #CLKCTL_CSCDR1] + orr r1, r1, #0x3f + eor r1, r1, #0x3f + orr r1, r1, #0x21 + str r1, [r0, #CLKCTL_CSCDR1] +#endif /* make sure divider effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 @@ -249,6 +261,7 @@ .globl lowlevel_init lowlevel_init: +#if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #(1 << 23) @@ -256,6 +269,7 @@ lowlevel_init: ldr r1, [r0, #0x4] orr r1, r1, #(1 << 23) str r1, [r0, #0x4] +#endif init_l2cc @@ -269,9 +283,12 @@ lowlevel_init: mov pc,lr /* Board level setting value */ -DDR_PERCHARGE_CMD: .word 0x04008008 -DDR_REFRESH_CMD: .word 0x00008010 -DDR_LMR1_W: .word 0x00338018 -DDR_LMR_CMD: .word 0xB2220000 -DDR_TIMING_W: .word 0xB02567A9 -DDR_MISC_W: .word 0x000A0104 +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 2900119..09500b3 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -33,17 +33,20 @@ #include <fsl_esdhc.h> #endif -#if defined(CONFIG_MX51) -#define CPU_TYPE 0x51000 -#else +#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) #error "CPU_TYPE not defined" #endif u32 get_cpu_rev(void) { - int system_rev = CPU_TYPE; +#ifdef CONFIG_MX51 + int system_rev = 0x51000; +#else + int system_rev = 0x53000; +#endif int reg = __raw_readl(ROM_SI_REV); +#if defined(CONFIG_MX51) switch (reg) { case 0x02: system_rev |= CHIP_REV_1_1; @@ -57,11 +60,20 @@ u32 get_cpu_rev(void) case 0x20: system_rev |= CHIP_REV_3_0; break; - return system_rev; default: system_rev |= CHIP_REV_1_0; break; } +#else + switch (reg) { + case 0x20: + system_rev |= CHIP_REV_2_0; + break; + default: + system_rev |= CHIP_REV_1_0; + break; + } +#endif return system_rev; } diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h index afd2728..2258f2f 100644 --- a/arch/arm/include/asm/arch-mx5/asm-offsets.h +++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h @@ -37,7 +37,12 @@ #define CLKCTL_CCGR4 0x78 #define CLKCTL_CCGR5 0x7C #define CLKCTL_CCGR6 0x80 +#if defined(CONFIG_MX53) +#define CLKCTL_CCGR7 0x84 #define CLKCTL_CMEOR 0x84 +#elif defined(CONFIG_MX51) +#define CLKCTL_CMEOR 0x84 +#endif /* DPLL */ #define PLL_DP_CTL 0x00 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h old mode 100644 new mode 100755 index b45026d..8be7f4b --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -20,38 +20,36 @@ * MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MXC_MX51_H__ -#define __ASM_ARCH_MXC_MX51_H__ +#ifndef __ASM_ARCH_MX5_IMX_REGS_H__ +#define __ASM_ARCH_MX5_IMX_REGS_H__ -/* - * IRAM - */ +#if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define IRAM_SIZE 0x00020000 /* 128 KB */ -/* - * Graphics Memory of GPU - */ -#define GPU_BASE_ADDR 0x20000000 -#define GPU_CTRL_BASE_ADDR 0x30000000 #define IPU_CTRL_BASE_ADDR 0x40000000 -/* - * Debug - */ -#define DEBUG_BASE_ADDR 0x60000000 -#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) -#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) -#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) -#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) -#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) -#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) -#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) -#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) +#define SPBA0_BASE_ADDR 0x70000000 +#define AIPS1_BASE_ADDR 0x73F00000 +#define AIPS2_BASE_ADDR 0x83F00000 +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define NFC_BASE_ADDR_AXI 0xCFFF0000 +#elif defined(CONFIG_MX53) +#define IPU_CTRL_BASE_ADDR 0x18000000 +#define SPBA0_BASE_ADDR 0x50000000 +#define AIPS1_BASE_ADDR 0x53F00000 +#define AIPS2_BASE_ADDR 0x63F00000 +#define CSD0_BASE_ADDR 0x70000000 +#define CSD1_BASE_ADDR 0xB0000000 +#define NFC_BASE_ADDR_AXI 0xF7FF0000 +#define IRAM_BASE_ADDR 0xF8000000 +#else +#error "CPU_TYPE not defined" +#endif + +#define IRAM_SIZE 0x00020000 /* 128 KB */ /* * SPBA global module enabled #0 */ -#define SPBA0_BASE_ADDR 0x70000000 - #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) @@ -68,8 +66,6 @@ /* * AIPS 1 */ -#define AIPS1_BASE_ADDR 0x73F00000 - #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) @@ -91,11 +87,14 @@ #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) +#if defined(CONFIG_MX53) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#endif /* * AIPS 2 */ -#define AIPS2_BASE_ADDR 0x83F00000 - #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) @@ -129,26 +128,7 @@ #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) -#define TZIC_BASE_ADDR 0x8FFFC000 - /* - * Memory regions and CS - */ -#define CSD0_BASE_ADDR 0x90000000 -#define CSD1_BASE_ADDR 0xA0000000 -#define CS0_BASE_ADDR 0xB0000000 -#define CS1_BASE_ADDR 0xB8000000 -#define CS2_BASE_ADDR 0xC0000000 -#define CS3_BASE_ADDR 0xC8000000 -#define CS4_BASE_ADDR 0xCC000000 -#define CS5_BASE_ADDR 0xCE000000 - -/* - * NFC - */ -#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ - -/*! * Number of GPIO port as defined in the IC Spec */ #define GPIO_PORT_NUM 4 @@ -311,4 +291,4 @@ struct fuse_bank1_regs { #endif /* __ASSEMBLER__*/ -#endif /* __ASM_ARCH_MXC_MX51_H__ */ +#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h index 0d91a24..760371b 100644 --- a/arch/arm/include/asm/arch-mx5/iomux.h +++ b/arch/arm/include/asm/arch-mx5/iomux.h @@ -70,108 +70,6 @@ typedef enum iomux_pad_config { PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ } iomux_pad_config_t; -/* various IOMUX input select register index */ -typedef enum iomux_input_select { - MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, - MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, - MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, - MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, - /* TO2 */ - MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, - MUX_IN_FEC_FEC_COL_SELECT_INPUT, - MUX_IN_FEC_FEC_CRS_SELECT_INPUT, - MUX_IN_FEC_FEC_MDI_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, - MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, - /* TO2 */ - MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, - MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, - MUX_INPUT_NUM_MUX, -} iomux_input_select_t; - /* various IOMUX input functions */ typedef enum iomux_input_config { INPUT_CTL_PATH0 = 0x0, diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h old mode 100644 new mode 100755 index a564fce..4e3a31b --- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h +++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h @@ -86,12 +86,22 @@ #define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) #define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) -#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_PAD_I PIN_TO_PAD_MASK + +#if defined(CONFIG_MX51) #define MUX_I_START 0x001C #define PAD_I_START 0x3F0 #define INPUT_CTL_START 0x8C4 -#define INPUT_CTL_START_TO1 0x928 #define MUX_I_END (PAD_I_START - 4) +#elif defined(CONFIG_MX53) +#define MUX_I_START 0x0020 +#define PAD_I_START 0x348 +#define INPUT_CTL_START 0x730 +#define MUX_I_END (PAD_I_START - 4) +#else +#error "CPU_TYPE not defined" +#endif #define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ @@ -115,7 +125,7 @@ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated * value is constructed based on the rules described above. */ -enum iomux_pins { +enum { MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), @@ -414,5 +424,458 @@ enum iomux_pins { MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), }; +enum { + MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348), + MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C), + MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350), + MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354), + MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358), + MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C), + MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360), + MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364), + MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368), + MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C), + MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370), + MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374), + MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378), + MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C), + MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380), + MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384), + MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388), + MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C), + MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390), + MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394), + MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398), + MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C), + MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0), + MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4), + MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8), + MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC), + MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0), + MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4), + MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8), + MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC), + MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0), + MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4), + MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8), + MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC), + MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0), + MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4), + MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8), + MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC), + MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0), + MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4), + MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8), + MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC), + MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0), + MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4), + MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8), + MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC), + MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400), + MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404), + MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408), + MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C), + MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410), + MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414), + MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418), + MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C), + MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420), + MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424), + MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428), + MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C), + MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430), + MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434), + MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438), + MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C), + MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440), + MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444), + MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448), + MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C), + MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450), + MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454), + MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458), + MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C), + MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460), + MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464), + MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468), + MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C), + MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470), + MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474), + MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478), + MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C), + MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480), + MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484), + MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488), + MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C), + MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490), + MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494), + MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498), + MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C), + MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0), + MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4), + MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8), + MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC), + MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0), + MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4), + MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8), + MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC), + MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0), + MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4), + MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8), + MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC), + MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0), + MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4), + MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8), + MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC), + MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0), + MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4), + MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8), + MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC), + MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0), + MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4), + MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8), + MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC), + MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500), + MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504), + MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508), + MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C), + MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510), + MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514), + MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518), + MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C), + MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520), + MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524), + MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528), + MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C), + MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530), + MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534), + MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538), + MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C), + MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I), + MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I), + MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I), + MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I), + MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I), + MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I), + MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I), + MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I), + MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I), + MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I), + MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540), + MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544), + MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548), + MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C), + MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550), + MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554), + MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558), + MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C), + MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560), + MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564), + MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568), + MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C), + MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570), + MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574), + MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578), + MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C), + MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580), + MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584), + MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588), + MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C), + MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590), + MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594), + MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598), + MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C), + MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0), + MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4), + MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8), + MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC), + MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0), + MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4), + MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8), + MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC), + MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0), + MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4), + MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8), + MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC), + MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0), + MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4), + MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8), + MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC), + MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0), + MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4), + MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8), + MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC), + MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0), + MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4), + MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8), + MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC), + MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600), + MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604), + MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608), + MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C), + MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610), + MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614), + MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618), + MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C), + MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620), + MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624), + MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628), + MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C), + MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630), + MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634), + MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638), + MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C), + MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640), + MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644), + MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648), + MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C), + MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650), + MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654), + MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658), + MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C), + MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660), + MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664), + MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668), + MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C), + MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670), + MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674), + MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678), + MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C), + MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680), + MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684), + MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688), + MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C), + MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690), + MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694), + MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698), + MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C), + MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0), + MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4), + MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8), + MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC), + MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0), + MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4), + MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8), + MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC), + MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0), + MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4), + MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8), + MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC), + MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0), + MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4), + MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8), + MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC), + MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0), + MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4), + MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8), + MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC), + MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0), + MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4), + MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC), + MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708), + MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C), + MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710), + MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714), + MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718), + MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C), + MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720), + MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724), + MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728), + MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C), +}; +/* various IOMUX input select register index */ +typedef enum iomux_input_select { + MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MX51_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MX51_CCM_IPP_DI1_CLK_SELECT_INPUT, + MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX51_CSPI_IPP_IND_MISO_SELECT_INPUT, + MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MX51_FEC_FEC_COL_SELECT_INPUT, + MX51_FEC_FEC_CRS_SELECT_INPUT, + MX51_FEC_FEC_MDI_SELECT_INPUT, + MX51_FEC_FEC_RDATA_0_SELECT_INPUT, + MX51_FEC_FEC_RDATA_1_SELECT_INPUT, + MX51_FEC_FEC_RDATA_2_SELECT_INPUT, + MX51_FEC_FEC_RDATA_3_SELECT_INPUT, + MX51_FEC_FEC_RX_CLK_SELECT_INPUT, + MX51_FEC_FEC_RX_DV_SELECT_INPUT, + MX51_FEC_FEC_RX_ER_SELECT_INPUT, + MX51_FEC_FEC_TX_CLK_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MX51_I2C1_IPP_SCL_IN_SELECT_INPUT, + MX51_I2C1_IPP_SDA_IN_SELECT_INPUT, + MX51_I2C2_IPP_SCL_IN_SELECT_INPUT, + MX51_I2C2_IPP_SDA_IN_SELECT_INPUT, + MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + MX51_KPP_IPP_IND_COL_6_SELECT_INPUT, + MX51_KPP_IPP_IND_COL_7_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MX51PUT_NUM_MUX, + /* MX53 */ + MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT, + MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I, + MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I, + MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT, + MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT, + MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT, + MX53_CCM_IPP_DI1_CLK_SELECT_INPUT, + MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT, + MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT, + MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX53_CSPI_IPP_IND_MISO_SELECT_INPUT, + MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT, + MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT, + MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT, + MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT, + MX53_ESAI1_IPP_IND_FST_SELECT_INPUT, + MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT, + MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT, + MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT, + MX53_FEC_FEC_COL_SELECT_INPUT, + MX53_FEC_FEC_MDI_SELECT_INPUT, + MX53_FEC_FEC_RX_CLK_SELECT_INPUT, + MX53_FIRI_IPP_IND_RXD_SELECT_INPUT, + MX53_GPC_PMIC_RDY_SELECT_INPUT, + MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, + MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, + MX53_I2C3_IPP_SCL_IN_SELECT_INPUT, + MX53_I2C3_IPP_SDA_IN_SELECT_INPUT, + MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT, + MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT, + MX53_KPP_IPP_IND_COL_5_SELECT_INPUT, + MX53_KPP_IPP_IND_COL_6_SELECT_INPUT, + MX53_KPP_IPP_IND_COL_7_SELECT_INPUT, + MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MX53_MLB_MLBCLK_IN_SELECT_INPUT, + MX53_MLB_MLBDAT_IN_SELECT_INPUT, + MX53_MLB_MLBSIG_IN_SELECT_INPUT, + MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT, + MX53_SDMA_EVENTS_14_SELECT_INPUT, + MX53_SDMA_EVENTS_15_SELECT_INPUT, + MX53_SPDIF_SPDIF_IN1_SELECT_INPUT, + MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, + MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, + MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT, +} iomux_input_select_t; + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h old mode 100644 new mode 100755 index b4e5738..3d6d390 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -24,8 +24,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/imx-regs.h> - /* High Level Configuration Options */ #define CONFIG_MX51 /* in a mx51 */ @@ -37,6 +35,7 @@ #define CONFIG_L2_OFF +#include <asm/arch/imx-regs.h> /* * Disabled for now due to build problems under Debian and a significant * increase in the final file size: 144260 vs. 109536 Bytes. diff --git a/include/configs/vision2.h b/include/configs/vision2.h index a5c116b..4c8e7fa 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -24,11 +24,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/imx-regs.h> #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_L2_OFF +#include <asm/arch/imx-regs.h> + #define CONFIG_SYS_MX5_HCLK 24000000 #define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor 2010-12-29 12:38 ` [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor Jason Liu @ 2010-12-30 12:09 ` Stefano Babic 2010-12-31 3:00 ` Jason Liu 0 siblings, 1 reply; 18+ messages in thread From: Stefano Babic @ 2010-12-30 12:09 UTC (permalink / raw) To: u-boot On 12/29/2010 01:38 PM, Jason Liu wrote: > Add initial support for Freescale MX53 processor, > > - Add the iomux support and the pin definition, > - Add the regs definition, clean up some unused def from mx51, > - Add the low level init support, make use the freq input of setup_pll macro Hi Jason, > diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h > index afd2728..2258f2f 100644 > --- a/arch/arm/include/asm/arch-mx5/asm-offsets.h > +++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h > @@ -37,7 +37,12 @@ > #define CLKCTL_CCGR4 0x78 > #define CLKCTL_CCGR5 0x7C > #define CLKCTL_CCGR6 0x80 > +#if defined(CONFIG_MX53) > +#define CLKCTL_CCGR7 0x84 > #define CLKCTL_CMEOR 0x84 > +#elif defined(CONFIG_MX51) > +#define CLKCTL_CMEOR 0x84 > +#endif It seems to me that CLKCTL_CMEOR should be dropped in the CONFIG_MX53 case, as its offset is reserved for CLKCTL_CCGR7. > -/*! > * Number of GPIO port as defined in the IC Spec > */ > #define GPIO_PORT_NUM 4 I see now that GPIO_PORT_NUM seems superfluous, and it is not used in any part of code. Please drop it :-) Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor 2010-12-30 12:09 ` Stefano Babic @ 2010-12-31 3:00 ` Jason Liu 0 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-31 3:00 UTC (permalink / raw) To: u-boot Hi, Stefano, 2010/12/30 Stefano Babic <sbabic@denx.de>: > On 12/29/2010 01:38 PM, Jason Liu wrote: >> Add initial support for Freescale MX53 processor, >> >> - Add the iomux support and the pin definition, >> - Add the regs definition, clean up some unused def from mx51, >> - Add the low level init support, make use the freq input of setup_pll macro > > Hi Jason, > >> diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h >> index afd2728..2258f2f 100644 >> --- a/arch/arm/include/asm/arch-mx5/asm-offsets.h >> +++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h >> @@ -37,7 +37,12 @@ >> ?#define CLKCTL_CCGR4 ? ? ? ? ? ?0x78 >> ?#define CLKCTL_CCGR5 ? ? ? ? ? ?0x7C >> ?#define CLKCTL_CCGR6 ? ? ? ? ? ?0x80 >> +#if defined(CONFIG_MX53) >> +#define CLKCTL_CCGR7 ? ? ? ? ? ?0x84 >> ?#define CLKCTL_CMEOR ? ? ? ? ? ?0x84 >> +#elif defined(CONFIG_MX51) >> +#define CLKCTL_CMEOR ? ? ? ? ? ?0x84 >> +#endif > > It seems to me that CLKCTL_CMEOR should be dropped in the CONFIG_MX53 > case, as its offset is reserved for CLKCTL_CCGR7. I will fix the CLKCTL_CMEOR offset in MX53. Thanks for the careful review. > >> -/*! >> ? * Number of GPIO port as defined in the IC Spec >> ? */ >> ?#define GPIO_PORT_NUM ? ? ? ? ? ? ? ?4 > > I see now that GPIO_PORT_NUM seems superfluous, and it is not used in > any part of code. Please drop it :-) OK, > > Best regards, > Stefano Babic > > -- > ===================================================================== > DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de > ===================================================================== > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 2/8] fec_mxc: add support for MX53 processor 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 2/3] imximage: Add MX53 boot image support Jason Liu ` (6 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot This patch add FEC support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com> --- drivers/net/fec_mxc.c | 2 +- drivers/net/fec_mxc.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0d0f392..652ced4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -354,7 +354,7 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); -#ifdef CONFIG_MX25 +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /* * setup the MII gasket for RMII mode diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 5d0d69d..1ba5161 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -147,7 +147,7 @@ struct ethernet_regs { uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ -#ifdef CONFIG_MX25 +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ @@ -204,7 +204,7 @@ struct ethernet_regs { #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ -#ifdef CONFIG_MX25 +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) /* defines for MIIGSK */ /* RMII frequency control: 0=50MHz, 1=5MHz */ #define MIIGSK_CFGR_FRCONT (1 << 6) -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 2/3] imximage: Add MX53 boot image support 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 2/8] fec_mxc: add " Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-29 12:49 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board Jason Liu ` (5 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot This patch add the MX53 boot image support. This patch has been tested on Freescale MX53EVK board and MX51EVK board. Signed-off-by: Jason Liu <r64343@freescale.com> --- Changes for v2: - Address the following comments from Stefano, - Get rid of #ifdef in the imximage.h and .c file and use the runtime check for imximage version - Document the IMXIMAGE_VERSION definiton in doc/README.imximage - Move mx53evk/config.mk and mx53evk/imximage.cfg to MX53EVK board support patch. --- board/freescale/mx51evk/imximage.cfg | 4 + board/ttcontrol/vision2/imximage_hynix.cfg | 4 + doc/README.imximage | 10 +- tools/imximage.c | 357 ++++++++++++++++++++++------ tools/imximage.h | 98 ++++++-- 5 files changed, 382 insertions(+), 91 deletions(-) diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg index a875e8f..11825fb 100644 --- a/board/freescale/mx51evk/imximage.cfg +++ b/board/freescale/mx51evk/imximage.cfg @@ -25,6 +25,10 @@ # # The syntax is taken as close as possible with the kwbimage +# Imximage version + +IMXIMAGE_VERSION 1 + # Boot Device : one of # spi, sd (the board has no nand neither onenand) diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg index ed531db..cdc533d 100644 --- a/board/ttcontrol/vision2/imximage_hynix.cfg +++ b/board/ttcontrol/vision2/imximage_hynix.cfg @@ -28,6 +28,10 @@ # # The syntax is taken as close as possible with the kwbimage +# Imximage version + +IMXIMAGE_VERSION 2 + # Boot Device : one of # spi, nand, onenand, sd diff --git a/doc/README.imximage b/doc/README.imximage index 3378f7e..48ac466 100644 --- a/doc/README.imximage +++ b/doc/README.imximage @@ -57,6 +57,11 @@ Configuration command line syntax: 2. Following are the valid command strings and associated data strings:- Command string data string -------------- ----------- + IMXIMAGE_VERSION 1/2 + 1 is for mx25/mx35/mx51 compatible, + 2 is for mx53 compatible, + others is invalid and error is generated. + BOOT_FROM nand/spi/sd/onenand Example: BOOT_FROM spi @@ -69,8 +74,9 @@ Configuration command line syntax: Example (write to IOMUXC): DATA 4 0x73FA88a0 0x200 -The processor support up to 60 register programming commands. An error -is generated if more commands are found in the configuration file. +The processor support up to 60 register programming commands for IMXIMAGE_VERSION 1 +and 121 register programming commands for IMXIMAGE_VERSION 2. +An error is generated if more commands are found in the configuration file. 3. All commands are optional to program. diff --git a/tools/imximage.c b/tools/imximage.c index 39f89c2..2bbc4a6 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -36,6 +36,7 @@ * Supported commands for configuration file */ static table_entry_t imximage_cmds[] = { + {CMD_IMXIMAGE_VERSION, "IMXIMAGE_VERSION", "imximage version", }, {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, {CMD_DATA, "DATA", "Reg Write Data", }, {-1, "", "", }, @@ -53,6 +54,14 @@ static table_entry_t imximage_bootops[] = { {-1, "", "Invalid", }, }; +/* + * IMXIMAGE version definition for i.MX chips + */ +static table_entry_t imximage_versions[] = { + {IMXIMAGE_V1, "", " (i.MX25/35/51 compatible)", }, + {IMXIMAGE_V2, "", " (i.MX53 compatible)", }, + {-1, "", " (Invalid)", }, +}; static struct imx_header imximage_header; @@ -71,6 +80,128 @@ static uint32_t get_cfg_value(char *token, char *name, int linenr) return value; } +static void err_imximage_version(int version) +{ + fprintf(stderr, + "Error: Unsuported imximage version:%d\n", version); + + exit(EXIT_FAILURE); +} + +static void set_dcd_value_v1(struct imx_header *imxhdr, char *name, int lineno, + int fld, uint32_t value, uint32_t off) +{ + dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table; + + switch (fld) { + case CFG_REG_SIZE: + /* Byte, halfword, word */ + if ((value != 1) && (value != 2) && (value != 4)) { + fprintf(stderr, "Error: %s[%d] - " + "Invalid register size " "(%d)\n", + name, lineno, value); + exit(EXIT_FAILURE); + } + dcd_v1->addr_data[off].type = value; + break; + case CFG_REG_ADDRESS: + dcd_v1->addr_data[off].addr = value; + break; + case CFG_REG_VALUE: + dcd_v1->addr_data[off].value = value; + break; + default: + break; + + } +} + +static void set_dcd_value_v2(struct imx_header *imxhdr, char *name, int lineno, + int fld, uint32_t value, uint32_t off) +{ + dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table; + + switch (fld) { + case CFG_REG_ADDRESS: + dcd_v2->addr_data[off].addr = cpu_to_be32(value); + break; + case CFG_REG_VALUE: + dcd_v2->addr_data[off].value = cpu_to_be32(value); + break; + default: + break; + + } +} + +static void set_dcd_value(struct imx_header *imxhdr, char *name, int lineno, + int fld, uint32_t value, uint32_t off) +{ + switch (imxhdr->imximage_version) { + case IMXIMAGE_V1: + set_dcd_value_v1(imxhdr, name, lineno, fld, value, off); + break; + case IMXIMAGE_V2: + set_dcd_value_v2(imxhdr, name, lineno, fld, value, off); + break; + default: + err_imximage_version(imxhdr->imximage_version); + break; + } +} + +static void set_dcd_rest_v1(struct imx_header *imxhdr, uint32_t dcd_len, + char *name, int lineno) +{ + dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table; + + if (dcd_len > MAX_HW_CFG_SIZE_V1) { + fprintf(stderr, "Error: %s[%d] -" + "DCD table exceeds maximum size(%d)\n", + name, lineno, MAX_HW_CFG_SIZE_V1); + } + + dcd_v1->preamble.barker = DCD_BARKER; + dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t); +} + +static void set_dcd_rest_v2(struct imx_header *imxhdr, uint32_t dcd_len, + char *name, int lineno) +{ + dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table; + + if (dcd_len > MAX_HW_CFG_SIZE_V2) { + fprintf(stderr, "Error: %s[%d] -" + "DCD table exceeds maximum size(%d)\n", + name, lineno, MAX_HW_CFG_SIZE_V2); + } + + dcd_v2->header.tag = DCD_HEADER_TAG; + dcd_v2->header.length = cpu_to_be16( + dcd_len * sizeof(dcd_addr_data_t) + 8); + dcd_v2->header.version = DCD_VERSION; + dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG; + dcd_v2->write_dcd_command.length = cpu_to_be16( + dcd_len * sizeof(dcd_addr_data_t) + 4); + dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM; +} + +static void set_dcd_rest(struct imx_header *imxhdr, uint32_t dcd_len, + char *name, int lineno) +{ + switch (imxhdr->imximage_version) { + case IMXIMAGE_V1: + set_dcd_rest_v1(imxhdr, dcd_len, name, lineno); + break; + case IMXIMAGE_V2: + set_dcd_rest_v2(imxhdr, dcd_len, name, lineno); + break; + default: + err_imximage_version(imxhdr->imximage_version); + break; + } +} + static int imximage_check_image_types(uint8_t type) { if (type == IH_TYPE_IMXIMAGE) @@ -82,44 +213,91 @@ static int imximage_check_image_types(uint8_t type) static int imximage_verify_header(unsigned char *ptr, int image_size, struct mkimage_params *params) { - struct imx_header *imx_hdr = (struct imx_header *) ptr; - flash_header_t *hdr = &imx_hdr->fhdr; + flash_header_v1_t *fhdr = &imx_hdr->header.hdr_v1.fhdr; + + if (imx_hdr->imximage_version != IMXIMAGE_V1) + return 0; /* Only a few checks can be done: search for magic numbers */ - if (hdr->app_code_barker != APP_CODE_BARKER) + if (fhdr->app_code_barker != APP_CODE_BARKER) return -FDT_ERR_BADSTRUCTURE; - if (imx_hdr->dcd_table.preamble.barker != DCD_BARKER) + if (imx_hdr->header.hdr_v1.dcd_table.preamble.barker != DCD_BARKER) return -FDT_ERR_BADSTRUCTURE; return 0; } -static void imximage_print_header(const void *ptr) +static void imximage_print_header_v1(struct imx_header *imx_hdr) { - struct imx_header *imx_hdr = (struct imx_header *) ptr; - flash_header_t *hdr = &imx_hdr->fhdr; - uint32_t size; - uint32_t length; - dcd_t *dcd = &imx_hdr->dcd_table; + imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1; + flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr; + dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table; + uint32_t size, length; - size = imx_hdr->dcd_table.preamble.length; - if (size > (MAX_HW_CFG_SIZE * sizeof(dcd_type_addr_data_t))) { + size = dcd_v1->preamble.length; + if (size > (MAX_HW_CFG_SIZE_V1 * sizeof(dcd_type_addr_data_t))) { fprintf(stderr, "Error: Image corrupt DCD size %d exceed maximum %d\n", (uint32_t)(size / sizeof(dcd_type_addr_data_t)), - MAX_HW_CFG_SIZE); + MAX_HW_CFG_SIZE_V1); exit(EXIT_FAILURE); } - length = dcd->preamble.length / sizeof(dcd_type_addr_data_t); + length = dcd_v1->preamble.length / sizeof(dcd_type_addr_data_t); + + printf("Image Type: Freescale IMX Boot Image\n"); + printf("Image Ver: %x", (uint32_t)imx_hdr->imximage_version); + printf("%s\n", get_table_entry_name(imximage_versions, + NULL, imx_hdr->imximage_version)); + printf("Data Size: "); + genimg_print_size(dcd_v1->addr_data[length].type); + printf("Load Address: %08x\n", (uint32_t)fhdr_v1->app_dest_ptr); + printf("Entry Point: %08x\n", (uint32_t)fhdr_v1->app_code_jump_vector); +} + +static void imximage_print_header_v2(struct imx_header *imx_hdr) +{ + imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2; + flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr; + dcd_v2_t *dcd_v2 = &hdr_v2->dcd_table; + uint32_t size; + + size = be16_to_cpu(dcd_v2->header.length) - 8; + if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) { + fprintf(stderr, + "Error: Image corrupt DCD size %d exceed maximum %d\n", + (uint32_t)(size / sizeof(dcd_addr_data_t)), + MAX_HW_CFG_SIZE_V2); + exit(EXIT_FAILURE); + } printf("Image Type: Freescale IMX Boot Image\n"); + printf("Image Ver: %x", (uint32_t)imx_hdr->imximage_version); + printf("%s\n", get_table_entry_name(imximage_versions, + NULL, imx_hdr->imximage_version)); printf("Data Size: "); - genimg_print_size(dcd->addr_data[length].type); - printf("Load Address: %08x\n", (unsigned int)hdr->app_dest_ptr); - printf("Entry Point: %08x\n", (unsigned int)hdr->app_code_jump_vector); + genimg_print_size(hdr_v2->boot_data.size); + printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr); + printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry); +} + +static void imximage_print_header(const void *ptr) +{ + struct imx_header *imx_hdr = (struct imx_header *) ptr; + + switch (imx_hdr->imximage_version) { + case IMXIMAGE_V1: + imximage_print_header_v1(imx_hdr); + break; + case IMXIMAGE_V2: + imximage_print_header_v2(imx_hdr); + break; + default: + err_imximage_version(imx_hdr->imximage_version); + break; + } } static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name) @@ -131,7 +309,6 @@ static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name) int fld, value; size_t len; int dcd_len = 0; - dcd_t *dcd = &imxhdr->dcd_table; int32_t cmd; fd = fopen(name, "r"); @@ -176,6 +353,11 @@ static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name) break; case CFG_REG_SIZE: switch (cmd) { + case CMD_IMXIMAGE_VERSION: + imxhdr->imximage_version = + get_cfg_value(token, + name, lineno); + break; case CMD_BOOT_FROM: /* Get flash header offset */ imxhdr->flash_offset = @@ -195,92 +377,131 @@ static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name) case CMD_DATA: value = get_cfg_value(token, name, lineno); - - /* Byte, halfword, word */ - if ((value != 1) && - (value != 2) && (value != 4)) { - fprintf(stderr, - "Error: %s[%d] - " - "Invalid register size " - "(%d)\n", - name, lineno, value); - exit(EXIT_FAILURE); - } - dcd->addr_data[dcd_len].type = value; + set_dcd_value(imxhdr, name, lineno, + fld, value, dcd_len); break; } case CFG_REG_ADDRESS: - if (cmd == CMD_DATA) - dcd->addr_data[dcd_len].addr = - get_cfg_value(token, + if (cmd == CMD_DATA) { + value = get_cfg_value(token, name, lineno); + set_dcd_value(imxhdr, name, lineno, + fld, value, dcd_len); + } break; case CFG_REG_VALUE: if (cmd == CMD_DATA) { - dcd->addr_data[dcd_len].value = - get_cfg_value(token, + value = get_cfg_value(token, name, lineno); + set_dcd_value(imxhdr, name, lineno, + fld, value, dcd_len); dcd_len++; } break; } } - if (dcd_len > MAX_HW_CFG_SIZE) { - fprintf(stderr, - "Error: %s[%d] -" - "DCD table exceeds maximum size(%d)\n", - name, lineno, MAX_HW_CFG_SIZE); - } } - dcd->preamble.barker = DCD_BARKER; - dcd->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t); - fclose(fd); + set_dcd_rest(imxhdr, dcd_len, name, lineno); + + fclose(fd); return dcd_len; } -static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) +static void imximage_set_header_v1(struct imx_header *imxhdr, uint32_t dcd_len, + struct stat *sbuf, + struct mkimage_params *params) { - struct imx_header *hdr = (struct imx_header *)ptr; - flash_header_t *fhdr = &hdr->fhdr; - int dcd_len; - dcd_t *dcd = &hdr->dcd_table; + imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1; + flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr; + dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table; uint32_t base_offset; /* Set default offset */ - hdr->flash_offset = FLASH_OFFSET_STANDARD; + imxhdr->flash_offset = FLASH_OFFSET_STANDARD; /* Set magic number */ - fhdr->app_code_barker = APP_CODE_BARKER; + fhdr_v1->app_code_barker = APP_CODE_BARKER; - /* Parse dcd configuration file */ - dcd_len = imximage_parse_cfg_file(hdr, params->imagename); - - fhdr->app_dest_ptr = params->addr; - fhdr->app_dest_ptr = params->ep - hdr->flash_offset - + fhdr_v1->app_dest_ptr = params->addr; + fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset - sizeof(struct imx_header); - fhdr->app_code_jump_vector = params->ep; + fhdr_v1->app_code_jump_vector = params->ep; - base_offset = fhdr->app_dest_ptr + hdr->flash_offset ; - fhdr->dcd_ptr_ptr = (uint32_t) (offsetof(flash_header_t, dcd_ptr) - - offsetof(flash_header_t, app_code_jump_vector) + + base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ; + fhdr_v1->dcd_ptr_ptr = + (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) - + offsetof(flash_header_v1_t, app_code_jump_vector) + base_offset); - fhdr->dcd_ptr = base_offset + - offsetof(struct imx_header, dcd_table); + fhdr_v1->dcd_ptr = base_offset + + offsetof(imx_header_v1_t, dcd_table); /* The external flash header must be at the end of the DCD table */ - dcd->addr_data[dcd_len].type = sbuf->st_size + - hdr->flash_offset + + dcd_v1->addr_data[dcd_len].type = sbuf->st_size + + imxhdr->flash_offset + sizeof(struct imx_header); /* Security feature are not supported */ - fhdr->app_code_csf = 0; - fhdr->super_root_key = 0; + fhdr_v1->app_code_csf = 0; + fhdr_v1->super_root_key = 0; +} + +static void imximage_set_header_v2(struct imx_header *imxhdr, + struct stat *sbuf, + struct mkimage_params *params) +{ + imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2; + flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr; + + /* Set default offset */ + imxhdr->flash_offset = FLASH_OFFSET_STANDARD; + + /* Set magic number */ + fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */ + fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t)); + fhdr_v2->header.version = IVT_VERSION; /* 0x40 */ + fhdr_v2->entry = params->ep; + fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0; + fhdr_v2->self = params->ep - sizeof(struct imx_header); + + fhdr_v2->dcd_ptr = fhdr_v2->self + + offsetof(imx_header_v2_t, dcd_table); + + fhdr_v2->boot_data_ptr = fhdr_v2->self + + offsetof(imx_header_v2_t, boot_data); + + hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset; + hdr_v2->boot_data.size = sbuf->st_size + + imxhdr->flash_offset + + sizeof(struct imx_header); + + /* Security feature are not supported */ + fhdr_v2->csf = 0; +} +static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct imx_header *imxhdr = (struct imx_header *)ptr; + uint32_t dcd_len; + + /* Parse dcd configuration file */ + dcd_len = imximage_parse_cfg_file(imxhdr, params->imagename); + + switch (imxhdr->imximage_version) { + case IMXIMAGE_V1: + imximage_set_header_v1(imxhdr, dcd_len, sbuf, params); + break; + case IMXIMAGE_V2: + imximage_set_header_v2(imxhdr, sbuf, params); + break; + default: + err_imximage_version(imxhdr->imximage_version); + break; + } } int imximage_check_params(struct mkimage_params *params) @@ -309,7 +530,7 @@ int imximage_check_params(struct mkimage_params *params) * imximage parameters */ static struct image_type_params imximage_params = { - .name = "Freescale i.MX 51 Boot Image support", + .name = "Freescale i.MX 5x Boot Image support", .header_size = sizeof(struct imx_header), .hdr = (void *)&imximage_header, .check_image_type = imximage_check_image_types, diff --git a/tools/imximage.h b/tools/imximage.h index b4d926d..67b9022 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -24,12 +24,14 @@ #ifndef _IMXIMAGE_H_ #define _IMXIMAGE_H_ -#define MAX_HW_CFG_SIZE 60 /* Max number of registers imx can set */ -#define MAX_EXP_SIZE 4 +#include <config.h> + +#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */ +#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ #define APP_CODE_BARKER 0xB1 #define DCD_BARKER 0xB17219E9 -#define HEADER_OFFSET 0x400 +#define HEADER_OFFSET 0x400 #define CMD_DATA_STR "DATA" #define FLASH_OFFSET_STANDARD 0x400 @@ -38,8 +40,16 @@ #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD #define FLASH_OFFSET_ONENAND 0x100 +#define IVT_HEADER_TAG 0xD1 +#define IVT_VERSION 0x40 +#define DCD_HEADER_TAG 0xD2 +#define DCD_COMMAND_TAG 0xCC +#define DCD_VERSION 0x40 +#define DCD_COMMAND_PARAM 0x4 + enum imximage_cmd { CMD_INVALID, + CMD_IMXIMAGE_VERSION, CMD_BOOT_FROM, CMD_DATA }; @@ -52,13 +62,10 @@ enum imximage_fld_types { CFG_REG_VALUE }; -typedef struct { - uint8_t rsa_exponent[MAX_EXP_SIZE]; /* RSA public exponent */ - uint8_t *rsa_modulus; /* RSA modulus pointer */ - uint16_t exponent_size; /* Exponent size (bytes) */ - uint16_t modulus_size; /* Modulus size (bytes) */ - uint8_t init_flag; /* key initialized */ -} hab_rsa_public_key; +enum imximage_version { + IMXIMAGE_V1 = 1, + IMXIMAGE_V2 +}; typedef struct { uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */ @@ -73,8 +80,8 @@ typedef struct { typedef struct { dcd_preamble_t preamble; - dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE]; -} dcd_t; + dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1]; +} dcd_v1_t; typedef struct { uint32_t app_code_jump_vector; @@ -84,22 +91,71 @@ typedef struct { uint32_t super_root_key; uint32_t dcd_ptr; uint32_t app_dest_ptr; -} flash_header_t; +} flash_header_v1_t; typedef struct { uint32_t length; /* Length of data to be read from flash */ } flash_cfg_parms_t; -struct imx_header { - flash_header_t fhdr; - dcd_t dcd_table; +typedef struct { + flash_header_v1_t fhdr; + dcd_v1_t dcd_table; flash_cfg_parms_t ext_header; - uint32_t flash_offset; -}; +} imx_header_v1_t; + +typedef struct { + uint32_t addr; + uint32_t value; +} dcd_addr_data_t; + +typedef struct { + uint8_t tag; + uint16_t length; + uint8_t version; +} __attribute__((packed)) ivt_header_t; -struct reg_config { - uint32_t raddr; - uint32_t rdata; +typedef struct { + uint8_t tag; + uint16_t length; + uint8_t param; +} __attribute__((packed)) write_dcd_command_t; + +typedef struct { + ivt_header_t header; + write_dcd_command_t write_dcd_command; + dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2]; +} dcd_v2_t; + +typedef struct { + uint32_t start; + uint32_t size; + uint32_t plugin; +} boot_data_t; + +typedef struct { + ivt_header_t header; + uint32_t entry; + uint32_t reserved1; + uint32_t dcd_ptr; + uint32_t boot_data_ptr; + uint32_t self; + uint32_t csf; + uint32_t reserved2; +} flash_header_v2_t; + +typedef struct { + flash_header_v2_t fhdr; + boot_data_t boot_data; + dcd_v2_t dcd_table; +} imx_header_v2_t; + +struct imx_header { + union { + imx_header_v1_t hdr_v1; + imx_header_v2_t hdr_v2; + } header; + uint32_t flash_offset; + uint32_t imximage_version; }; #endif /* _IMXIMAGE_H_ */ -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 2/3] imximage: Add MX53 boot image support 2010-12-29 12:38 ` [U-Boot] [PATCH v3 2/3] imximage: Add MX53 boot image support Jason Liu @ 2010-12-29 12:49 ` Jason Liu 0 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:49 UTC (permalink / raw) To: u-boot 2010/12/29 Jason Liu <r64343@freescale.com>: > This patch add the MX53 boot image support. > > This patch has been tested on Freescale MX53EVK board > and MX51EVK board. > > Signed-off-by: Jason Liu <r64343@freescale.com> > Please ignore the patch. Send it wrongly. Sorry for the noise. > > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu ` (2 preceding siblings ...) 2010-12-29 12:38 ` [U-Boot] [PATCH v3 2/3] imximage: Add MX53 boot image support Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-29 12:48 ` Jason Liu 2010-12-30 11:51 ` Stefano Babic 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/8] serial_mxc: add support for MX53 processor Jason Liu ` (4 subsequent siblings) 8 siblings, 2 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot Add initial support for MX53EVK board support. FEC, SD/MMC, UART, I2C, have been support. Signed-off-by: Jason Liu <r64343@freescale.com> --- Changes for v2: -Address the comments from Stefano, Albert and Wolfgang, -remove the ivt.S file and use imximage.cfg instead, -remove the ivt link to u-boot -Address the comments from Stefano, -Correct the copyright issue, -Use mxc_get_gpio() and mxc_set_gpio() accessors. -Get rid of system_rev, -use i2c enumeration value (0,1,..N) instead of BASE address, -use fsl_pmic i2c interface, -Add comments for why manage the pmic in a different way for TO2 -Remove the comments from configs/mx53evk.h, - /* - * Disabled for now due to build problems under Debian and a significant - * increase in the final file size: 144260 vs. 109536 Bytes. - */ -Address the comments from Wolfgang, -Move CONFIG_SYS_TEXT_BASE to board config file, -Remove the comments from configs/mx53evk.h - /* size in bytes reserved for initial data */ #define BOARD_LATE_INIT -Change the comments, * Hardware drivers to * UART drivers Changes for v3: - put uart and fec iomux setting to board_early_init_f so that uart can print out the early information such as uboot banner and cpuinfo etc. - put mxc_gpio patch into this commit according to Stefno comments, - Put maintainer name to ARM list according to Stefano comments, - Use Macro instead of constant value for PMIC accord to Stefano comments, - Remove CONFIG_I2C_MXC and BOARD_LATE_INIT accord to Stefano comments, - Add config.mk and imximage.cfg files to this patch as Stefano comments, --- MAINTAINERS | 4 + board/freescale/mx53evk/Makefile | 48 ++++ board/freescale/mx53evk/config.mk | 25 +++ board/freescale/mx53evk/imximage.cfg | 112 ++++++++++ board/freescale/mx53evk/mx53evk.c | 397 ++++++++++++++++++++++++++++++++++ boards.cfg | 1 + drivers/gpio/mxc_gpio.c | 9 +- include/configs/mx53evk.h | 217 +++++++++++++++++++ include/mc13892.h | 5 + 9 files changed, 816 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 0590ad9..698d401 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -555,6 +555,10 @@ Stefano Babic <sbabic@denx.de> mx51evk i.MX51 vision2 i.MX51 +Jason Liu <r64343@freescale.com> + + MX53evk i.MX53 + Enric Balletbo i Serra <eballetbo@iseebcn.com> igep0020 ARM ARMV7 (OMAP3xx SoC) diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile new file mode 100755 index 0000000..6b820f4 --- /dev/null +++ b/board/freescale/mx53evk/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx53evk.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx53evk/config.mk b/board/freescale/mx53evk/config.mk new file mode 100755 index 0000000..0153165 --- /dev/null +++ b/board/freescale/mx53evk/config.mk @@ -0,0 +1,25 @@ +# +# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg +ALL += $(obj)u-boot.imx + diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg new file mode 100644 index 0000000..49dc18d --- /dev/null +++ b/board/freescale/mx53evk/imximage.cfg @@ -0,0 +1,112 @@ +# +# (C Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Imximage version + +IMXIMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# Setting IOMUXC +DATA 4 0x53fa8554 0x00200000 +DATA 4 0x53fa8560 0x00200000 +DATA 4 0x53fa8594 0x00200000 +DATA 4 0x53fa8584 0x00200000 +DATA 4 0x53fa8558 0x00200040 +DATA 4 0x53fa8568 0x00200040 +DATA 4 0x53fa8590 0x00200040 +DATA 4 0x53fa857c 0x00200040 +DATA 4 0x53fa8564 0x00200040 +DATA 4 0x53fa8580 0x00200040 +DATA 4 0x53fa8570 0x00200000 +DATA 4 0x53fa8578 0x00200000 +DATA 4 0x53fa872c 0x00200000 +DATA 4 0x53fa8728 0x00200000 +DATA 4 0x53fa871c 0x00200000 +DATA 4 0x53fa8718 0x00200000 +DATA 4 0x53fa8574 0x00280000 +DATA 4 0x53fa8588 0x00280000 +DATA 4 0x53fa86f0 0x00280000 +DATA 4 0x53fa8720 0x00280000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa86f4 0x00000200 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8724 0x06000000 +DATA 4 0x63fd9088 0x34333936 +DATA 4 0x63fd9090 0x49434942 +DATA 4 0x63fd90F8 0x00000800 +DATA 4 0x63fd907c 0x01350138 +DATA 4 0x63fd9080 0x01380139 +DATA 4 0x63fd9018 0x00001710 +DATA 4 0x63fd9000 0xc4110000 +DATA 4 0x63fd900C 0x4d5122d2 +DATA 4 0x63fd9010 0x92d18a22 +DATA 4 0x63fd9014 0x00c70092 +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f000e +DATA 4 0x63fd9008 0x12272000 +DATA 4 0x63fd9004 0x00030012 +DATA 4 0x63fd901c 0x04008010 +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00008031 +DATA 4 0x63fd901c 0x0b5280b0 +DATA 4 0x63fd901c 0x04008010 +DATA 4 0x63fd901c 0x00008020 +DATA 4 0x63fd901c 0x00008020 +DATA 4 0x63fd901c 0x0a528030 +DATA 4 0x63fd901c 0x03c68031 +DATA 4 0x63fd901c 0x00448031 +DATA 4 0x63fd901c 0x04008018 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00008039 +DATA 4 0x63fd901c 0x0b528138 +DATA 4 0x63fd901c 0x04008018 +DATA 4 0x63fd901c 0x00008028 +DATA 4 0x63fd901c 0x00008028 +DATA 4 0x63fd901c 0x0a528038 +DATA 4 0x63fd901c 0x03c68039 +DATA 4 0x63fd901c 0x00448039 +DATA 4 0x63fd9020 0x00005800 +DATA 4 0x63fd9058 0x00033335 +DATA 4 0x63fd901c 0x00000000 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x53fa8004 0x00194005 diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c new file mode 100755 index 0000000..73bf53a --- /dev/null +++ b/board/freescale/mx53evk/mx53evk.c @@ -0,0 +1,397 @@ +/* + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <fsl_pmic.h> +#include <mxc_gpio.h> +#include <mc13892.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +static void setup_iomux_uart(void) +{ + /* UART1 RXD */ + mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D11, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); + + /* UART1 TXD */ + mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D10, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static void setup_i2c(unsigned int port_number) +{ + switch (port_number) { + case 0: + /* i2c1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* i2c1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + break; + case 1: + /* i2c2 SDA */ + mxc_request_iomux(MX53_PIN_KEY_ROW3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX53_PIN_KEY_COL3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + break; + default: + printf("Warning: Wrong I2C port number\n"); + break; + } +} + +void power_init(void) +{ + unsigned int val; + + /* Set VDDA to 1.25V */ + val = pmic_reg_read(REG_SW_2); + val &= ~SWX_OUT_MASK; + val |= SWX_OUT_1_25; + pmic_reg_write(REG_SW_2, val); + + /* + * Need increase VCC and VDDA to 1.3V + * according to MX53 IC TO2 datasheet. + */ + if (is_soc_rev(CHIP_REV_2_0) == 0) { + /* Set VCC to 1.3V for TO2 */ + val = pmic_reg_read(REG_SW_1); + val &= ~SWX_OUT_MASK; + val |= SWX_OUT_1_30; + pmic_reg_write(REG_SW_2, val); + + /* Set VDDA to 1.3V for TO2 */ + val = pmic_reg_read(REG_SW_2); + val &= ~SWX_OUT_MASK; + val |= SWX_OUT_1_30; + pmic_reg_write(REG_SW_2, val); + } +} + +static void setup_iomux_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); + + /*FEC_MDC*/ + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); + + /* FEC RXD1 */ + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC RXD0 */ + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC TXD1 */ + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); + + /* FEC TXD0 */ + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); + + /* FEC TX_EN */ + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); + + /* FEC TX_CLK */ + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC RX_ER */ + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC CRS */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC3_BASE_ADDR, 1}, +}; + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = mxc_gpio_get(77); /*GPIO3_13*/ + else + *cd = mxc_gpio_get(75); /*GPIO3_11*/ + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index; + s32 status = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_DA13, + IOMUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + break; + case 1: + mxc_request_iomux(MX53_PIN_ATA_RESET_B, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_IORDY, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA8, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA9, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA10, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA11, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA0, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA1, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA2, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA3, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_EIM_DA11, + IOMUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_late_init(void) +{ + setup_i2c(1); + power_init(); + + return 0; +} + +int checkboard(void) +{ + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + puts("Board: MX53EVK ["); + + cause = src_regs->srsr; + switch (cause) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + return 0; +} diff --git a/boards.cfg b/boards.cfg index dcd5a12..736e88e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -101,6 +101,7 @@ omap5912osk arm arm926ejs - ti edminiv2 arm arm926ejs - LaCie orion5x ca9x4_ct_vxp arm armv7 vexpress armltd mx51evk arm armv7 mx51evk freescale mx5 +mx53evk arm armv7 mx53evk freescale mx5 vision2 arm armv7 vision2 ttcontrol mx5 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 663141f..53a0673 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -24,7 +24,7 @@ #ifdef CONFIG_MX31 #include <asm/arch/mx31-regs.h> #endif -#ifdef CONFIG_MX51 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> #endif #include <asm/io.h> @@ -35,9 +35,14 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#ifdef CONFIG_MX51 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) [3] = GPIO4_BASE_ADDR, #endif +#if defined(CONFIG_MX53) + [4] = GPIO5_BASE_ADDR, + [5] = GPIO6_BASE_ADDR, + [6] = GPIO7_BASE_ADDR, +#endif }; int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h new file mode 100755 index 0000000..d6cf04e --- /dev/null +++ b/include/configs/mx53evk.h @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-EVK Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + /* High Level Configuration Options */ + +#define CONFIG_MX53 + +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_L2_OFF + +#include <asm/arch/imx-regs.h> + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX53_UART1 + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_MX53_PORT2 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* + * PMIC Configs + */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_I2C +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 + +/* + * MMC Configs + */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif /* __CONFIG_H */ diff --git a/include/mc13892.h b/include/mc13892.h index 61c3e6e..001cf56 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -160,4 +160,9 @@ /* Reg Power Control 2*/ #define WDIRESET (1 << 12) +/* SWx Output Volts */ +#define SWX_OUT_MASK 0x1F +#define SWX_OUT_1_25 0x1A +#define SWX_OUT_1_30 0X1C + #endif -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board Jason Liu @ 2010-12-29 12:48 ` Jason Liu 2010-12-30 11:51 ` Stefano Babic 1 sibling, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:48 UTC (permalink / raw) To: u-boot 2010/12/29 Jason Liu <r64343@freescale.com>: > Add initial support for MX53EVK board support. > FEC, SD/MMC, UART, I2C, have been support. > > Signed-off-by: Jason Liu <r64343@freescale.com> > Please ignore this patch. Send it wrongly. Sorry for the noise. > > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board Jason Liu 2010-12-29 12:48 ` Jason Liu @ 2010-12-30 11:51 ` Stefano Babic 2010-12-31 2:57 ` Jason Liu 1 sibling, 1 reply; 18+ messages in thread From: Stefano Babic @ 2010-12-30 11:51 UTC (permalink / raw) To: u-boot On 12/29/2010 01:38 PM, Jason Liu wrote: > Add initial support for MX53EVK board support. > FEC, SD/MMC, UART, I2C, have been support. > > Signed-off-by: Jason Liu <r64343@freescale.com> Hi Jason, > Changes for v3: > - put uart and fec iomux setting to board_early_init_f so that uart can print > out the early information such as uboot banner and cpuinfo etc. > - put mxc_gpio patch into this commit according to Stefno comments, This is not what I meant. I told to put the mxc_gpio patch into this patchset (as you have now done, [PATCH v3 4/8] mxc_gpio: add support for MX53 processor is in this patchset), but not to duplicate the patch inside this commit. In fact, I cannot apply your patches, as they are changing the same file. > > diff --git a/MAINTAINERS b/MAINTAINERS > index 0590ad9..698d401 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -555,6 +555,10 @@ Stefano Babic <sbabic@denx.de> > mx51evk i.MX51 > vision2 i.MX51 > > +Jason Liu <r64343@freescale.com> > + > + MX53evk i.MX53 > + > Enric Balletbo i Serra <eballetbo@iseebcn.com> Please maintain the list *alfabetically* sorted. > --- a/drivers/gpio/mxc_gpio.c > +++ b/drivers/gpio/mxc_gpio.c > @@ -24,7 +24,7 @@ > #ifdef CONFIG_MX31 > #include <asm/arch/mx31-regs.h> > #endif > -#ifdef CONFIG_MX51 Drop these changes from this patch, as we have them in the [PATCH v3 4/8]. > +/*********************************************************** > + * Command definition > + ***********************************************************/ Multiline comment, please fix globally in this file. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board 2010-12-30 11:51 ` Stefano Babic @ 2010-12-31 2:57 ` Jason Liu 0 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-31 2:57 UTC (permalink / raw) To: u-boot Hi, Stefano, 2010/12/30 Stefano Babic <sbabic@denx.de>: > On 12/29/2010 01:38 PM, Jason Liu wrote: >> Add initial support for MX53EVK board support. >> FEC, SD/MMC, UART, I2C, have been support. >> >> Signed-off-by: Jason Liu <r64343@freescale.com> > > Hi Jason, > >> Changes for v3: >> - put uart and fec iomux setting to board_early_init_f so that uart can print >> ? out the early information such as uboot banner and cpuinfo etc. >> - put mxc_gpio patch into this commit according to Stefno comments, > > This is not what I meant. I told to put the mxc_gpio patch into this > patchset (as you have now done, [PATCH v3 4/8] mxc_gpio: add support for > MX53 processor is in this patchset), but not to duplicate the patch > inside this commit. In fact, I cannot apply your patches, as they are > changing the same file. My bad. I will change it by removing it. > >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 0590ad9..698d401 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -555,6 +555,10 @@ Stefano Babic <sbabic@denx.de> >> ? ? ? mx51evk ? ? ? ? i.MX51 >> ? ? ? vision2 ? ? ? ? i.MX51 >> >> +Jason Liu <r64343@freescale.com> >> + >> + ? ? MX53evk ? ? ? ? i.MX53 >> + >> ?Enric Balletbo i Serra <eballetbo@iseebcn.com> > > Please maintain the list *alfabetically* sorted. OK, > > >> --- a/drivers/gpio/mxc_gpio.c >> +++ b/drivers/gpio/mxc_gpio.c >> @@ -24,7 +24,7 @@ >> ?#ifdef CONFIG_MX31 >> ?#include <asm/arch/mx31-regs.h> >> ?#endif >> -#ifdef CONFIG_MX51 > > Drop these changes from this patch, as we have them in the [PATCH v3 4/8]. Yes, I will do it. > >> +/*********************************************************** >> + * Command definition >> + ***********************************************************/ > > Multiline comment, please fix globally in this file. OK, I will fix it globally. > > Best regards, > Stefano Babic > > -- > ===================================================================== > DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de > ===================================================================== > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 3/8] serial_mxc: add support for MX53 processor 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu ` (3 preceding siblings ...) 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 4/8] mxc_gpio: " Jason Liu ` (3 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot This patch add UART support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com> --- drivers/serial/serial_mxc.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index f96b21f..805f4c5 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -56,6 +56,12 @@ #define UART_PHYS UART2_BASE_ADDR #elif defined(CONFIG_SYS_MX51_UART3) #define UART_PHYS UART3_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART1) +#define UART_PHYS UART1_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART2) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART3) +#define UART_PHYS UART3_BASE_ADDR #else #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" #endif -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 4/8] mxc_gpio: add support for MX53 processor 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu ` (4 preceding siblings ...) 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/8] serial_mxc: add support for MX53 processor Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 5/8] mxc_i2c: " Jason Liu ` (2 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot This patch add mxc_gpio support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com> --- Changes for v2 - put this patch into the same patchset with MX53 support as Stefano comments, --- drivers/gpio/mxc_gpio.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 663141f..53a0673 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -24,7 +24,7 @@ #ifdef CONFIG_MX31 #include <asm/arch/mx31-regs.h> #endif -#ifdef CONFIG_MX51 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> #endif #include <asm/io.h> @@ -35,9 +35,14 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#ifdef CONFIG_MX51 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) [3] = GPIO4_BASE_ADDR, #endif +#if defined(CONFIG_MX53) + [4] = GPIO5_BASE_ADDR, + [5] = GPIO6_BASE_ADDR, + [6] = GPIO7_BASE_ADDR, +#endif }; int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 5/8] mxc_i2c: add support for MX53 processor 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu ` (5 preceding siblings ...) 2010-12-29 12:38 ` [U-Boot] [PATCH v3 4/8] mxc_gpio: " Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 6/8] fsl_pmic: add I2C interface support Jason Liu 2010-12-29 12:47 ` [U-Boot] [PATCH v3 1/3] " Jason Liu 8 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot This patch add I2C support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com> --- Changes for v2: -address the comments of Heiko, add #if defined(CONFIG_MX31) to avoid break MX31 build. Move CONFIG_HARD_I2C to the top of the file and fix the error message from: #error "define CONFIG_SYS_I2C_PORT to use the I2C driver" to #error "define CONFIG_SYS_I2C_MXxx_PORTx to use the I2C driver" Changes for v3: -address the comments from Albert, change #ifdef to #if defined() for the sake of homogeneity --- drivers/i2c/mxc_i2c.c | 21 ++++++++++++++++++--- 1 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c old mode 100644 new mode 100755 index 8e10fbb..1ebec14 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -26,8 +26,14 @@ #if defined(CONFIG_HARD_I2C) +#if defined(CONFIG_MX31) #include <asm/arch/mx31.h> #include <asm/arch/mx31-regs.h> +#endif + +#if defined(CONFIG_MX53) +#include <asm/arch/clock.h> +#endif #define IADR 0x00 #define IFDR 0x04 @@ -47,7 +53,7 @@ #define I2SR_IIF (1 << 1) #define I2SR_RX_NO_AK (1 << 0) -#ifdef CONFIG_SYS_I2C_MX31_PORT1 +#if defined(CONFIG_SYS_I2C_MX31_PORT1) #define I2C_BASE 0x43f80000 #define I2C_CLK_OFFSET 26 #elif defined (CONFIG_SYS_I2C_MX31_PORT2) @@ -56,8 +62,12 @@ #elif defined (CONFIG_SYS_I2C_MX31_PORT3) #define I2C_BASE 0x43f84000 #define I2C_CLK_OFFSET 30 +#elif defined(CONFIG_SYS_I2C_MX53_PORT1) +#define I2C_BASE I2C1_BASE_ADDR +#elif defined(CONFIG_SYS_I2C_MX53_PORT2) +#define I2C_BASE I2C2_BASE_ADDR #else -#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver" +#error "define CONFIG_SYS_I2C_MXxx_PORTx to use the I2C driver" #endif #ifdef DEBUG @@ -72,11 +82,16 @@ static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, void i2c_init(int speed, int unused) { - int freq = mx31_get_ipg_clk(); + int freq; int i; +#if defined(CONFIG_MX31) + freq = mx31_get_ipg_clk(); /* start the required I2C clock */ __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET); +#else + freq = mxc_get_clock(MXC_IPG_PERCLK); +#endif for (i = 0; i < 0x1f; i++) if (freq / div[i] <= speed) -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 6/8] fsl_pmic: add I2C interface support 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu ` (6 preceding siblings ...) 2010-12-29 12:38 ` [U-Boot] [PATCH v3 5/8] mxc_i2c: " Jason Liu @ 2010-12-29 12:38 ` Jason Liu 2010-12-30 16:49 ` Stefano Babic 2010-12-29 12:47 ` [U-Boot] [PATCH v3 1/3] " Jason Liu 8 siblings, 1 reply; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:38 UTC (permalink / raw) To: u-boot This patch add I2C interface for fsl_pmic driver support Signed-off-by: Jason Liu <r64343@freescale.com> --- Changes for v2: - Address the comments from Stefano, - factor out the param_check in pmic_reg for both spi/i2c --- drivers/misc/fsl_pmic.c | 52 ++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c index 5ee1de1..b58854d 100644 --- a/drivers/misc/fsl_pmic.c +++ b/drivers/misc/fsl_pmic.c @@ -22,11 +22,55 @@ #include <config.h> #include <common.h> -#include <spi.h> #include <asm/errno.h> #include <linux/types.h> #include <fsl_pmic.h> +static int check_param(u32 reg, u32 write) +{ + if (reg > 63 || write > 1) { + printf("<reg num> = %d is invalid. Should be less then 63\n", + reg); + return -1; + } + + return 0; +} + +#ifdef CONFIG_FSL_PMIC_I2C +#include <i2c.h> +static int init_done; + +u32 pmic_reg(u32 reg, u32 val, u32 write) +{ + unsigned char buf[4] = { 0 }; + u32 ret_val = 0; + + if (check_param(reg, write)) + return -1; + + if (init_done == 0) { + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + init_done = 1; + } + + if (write) { + buf[0] = (val >> 16) & 0xff; + buf[1] = (val >> 8) & 0xff; + buf[2] = (val) & 0xff; + if (i2c_write(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3)) + return -1; + } else { + if (i2c_read(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3)) { + return -1; + ret_val = buf[0] << 16 | buf[1] << 8 | buf[2]; + } + } + + return ret_val; +} +#else /* SPI interface */ +#include <spi.h> static struct spi_slave *slave; struct spi_slave *pmic_spi_probe(void) @@ -55,11 +99,8 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) return -1; } - if (reg > 63 || write > 1) { - printf("<reg num> = %d is invalid. Should be less then 63\n", - reg); + if (check_param(reg, write)) return -1; - } if (spi_claim_bus(slave)) return -1; @@ -87,6 +128,7 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) spi_release_bus(slave); return cpu_to_be32(pmic_rx); } +#endif void pmic_reg_write(u32 reg, u32 value) { -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 6/8] fsl_pmic: add I2C interface support 2010-12-29 12:38 ` [U-Boot] [PATCH v3 6/8] fsl_pmic: add I2C interface support Jason Liu @ 2010-12-30 16:49 ` Stefano Babic 2010-12-31 3:54 ` Jason Liu 0 siblings, 1 reply; 18+ messages in thread From: Stefano Babic @ 2010-12-30 16:49 UTC (permalink / raw) To: u-boot On 12/29/2010 01:38 PM, Jason Liu wrote: > This patch add I2C interface for fsl_pmic driver support > > Signed-off-by: Jason Liu <r64343@freescale.com> > > --- > Changes for v2: > - Address the comments from Stefano, > - factor out the param_check in pmic_reg for both spi/i2c > --- > drivers/misc/fsl_pmic.c | 52 ++++++++++++++++++++++++++++++++++++++++++---- > 1 files changed, 47 insertions(+), 5 deletions(-) > Hi Jason, > + > + if (init_done == 0) { > + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); > + init_done = 1; > + } As I can see, i2c_init is called during initialization in arch/arm/lib/board.c. Why do we need to call it again ? > + if (write) { > + buf[0] = (val >> 16) & 0xff; > + buf[1] = (val >> 8) & 0xff; > + buf[2] = (val) & 0xff; > + if (i2c_write(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3)) > + return -1; > + } else { > + if (i2c_read(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3)) { > + return -1; > + ret_val = buf[0] << 16 | buf[1] << 8 | buf[2]; > + } I am wondering if it works. The line with ret_val is never reached. Do you tested it ? Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 6/8] fsl_pmic: add I2C interface support 2010-12-30 16:49 ` Stefano Babic @ 2010-12-31 3:54 ` Jason Liu 0 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-31 3:54 UTC (permalink / raw) To: u-boot Hi, Stefano, 2010/12/31 Stefano Babic <sbabic@denx.de>: > On 12/29/2010 01:38 PM, Jason Liu wrote: >> This patch add I2C interface for fsl_pmic driver support >> >> Signed-off-by: Jason Liu <r64343@freescale.com> >> >> --- >> Changes for v2: >> - Address the comments from Stefano, >> ? - factor out the param_check in pmic_reg for both spi/i2c >> --- >> ?drivers/misc/fsl_pmic.c | ? 52 ++++++++++++++++++++++++++++++++++++++++++---- >> ?1 files changed, 47 insertions(+), 5 deletions(-) >> > > Hi Jason, > >> + >> + ? ? if (init_done == 0) { >> + ? ? ? ? ? ? i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); >> + ? ? ? ? ? ? init_done = 1; >> + ? ? } > > As I can see, i2c_init is called during initialization in > arch/arm/lib/board.c. Why do we need to call it again ? Yes, I think, I can remove it. > >> + ? ? if (write) { >> + ? ? ? ? ? ? buf[0] = (val >> 16) & 0xff; >> + ? ? ? ? ? ? buf[1] = (val >> 8) & 0xff; >> + ? ? ? ? ? ? buf[2] = (val) & 0xff; >> + ? ? ? ? ? ? if (i2c_write(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3)) >> + ? ? ? ? ? ? ? ? ? ? return -1; >> + ? ? } else { >> + ? ? ? ? ? ? if (i2c_read(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3)) { >> + ? ? ? ? ? ? ? ? ? ? return -1; >> + ? ? ? ? ? ? ret_val = buf[0] << 16 | buf[1] << 8 | buf[2]; >> + ? ? ? ? ? ? } > > I am wondering if it works. The line with ret_val is never reached. Do > you tested it ? I have tested before. This patch of code is definitely wrong. I will fix it. Thanks for review. Happy New Year! > > Best regards, > Stefano Babic > > -- > ===================================================================== > DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de > ===================================================================== > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu ` (7 preceding siblings ...) 2010-12-29 12:38 ` [U-Boot] [PATCH v3 6/8] fsl_pmic: add I2C interface support Jason Liu @ 2010-12-29 12:47 ` Jason Liu 8 siblings, 0 replies; 18+ messages in thread From: Jason Liu @ 2010-12-29 12:47 UTC (permalink / raw) To: u-boot 2010/12/29 Jason Liu <r64343@freescale.com>: > This patch add I2C interface for fsl_pmic driver support > > Signed-off-by: Jason Liu <r64343@freescale.com> > Please ignore this patch. Send it wrongly. Sorry for the noise. > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2010-12-31 3:54 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-12-29 12:38 [U-Boot] [PATCH v3 1/3] fsl_pmic: add I2C interface support Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 1/8] MX5: Add initial support for MX53 processor Jason Liu 2010-12-30 12:09 ` Stefano Babic 2010-12-31 3:00 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 2/8] fec_mxc: add " Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 2/3] imximage: Add MX53 boot image support Jason Liu 2010-12-29 12:49 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/3] MX5:MX53: add initial support for MX53EVK board Jason Liu 2010-12-29 12:48 ` Jason Liu 2010-12-30 11:51 ` Stefano Babic 2010-12-31 2:57 ` Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 3/8] serial_mxc: add support for MX53 processor Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 4/8] mxc_gpio: " Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 5/8] mxc_i2c: " Jason Liu 2010-12-29 12:38 ` [U-Boot] [PATCH v3 6/8] fsl_pmic: add I2C interface support Jason Liu 2010-12-30 16:49 ` Stefano Babic 2010-12-31 3:54 ` Jason Liu 2010-12-29 12:47 ` [U-Boot] [PATCH v3 1/3] " Jason Liu
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