From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Wed, 12 Jan 2011 19:49:27 +0100 Subject: [U-Boot] [U-BOOT] [PATCH] arm: fix flush cache function on arm926ejs In-Reply-To: References: <1294760420-28029-1-git-send-email-leiwen@marvell.com> <4D2CB555.9070308@free.fr> Message-ID: <4D2DF7B7.7010500@free.fr> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Le 12/01/2011 05:31, Lei Wen a ?crit : > On Wed, Jan 12, 2011 at 12:27 PM, Lei Wen wrote: >> Hi Albert, >> >> On Wed, Jan 12, 2011 at 3:53 AM, Albert ARIBAUD wrote: >>> Hi, >>> >>> Le 11/01/2011 16:40, Lei Wen a ?crit : >>>> flush_cache function should only be called when the dcache is on. >>>> And original flush method for arm926ejs seems don't work, replace >>>> it with new version. >>>> >>>> Test on Marvell Pantheon pxa920 board with usb ether function. >>>> >>>> Signed-off-by: Lei Wen >>>> --- >>>> arch/arm/lib/cache.c | 8 ++++---- >>>> 1 files changed, 4 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c >>>> index 30686fe..b8d5eee 100644 >>>> --- a/arch/arm/lib/cache.c >>>> +++ b/arch/arm/lib/cache.c >>>> @@ -27,16 +27,16 @@ >>>> >>>> void flush_cache (unsigned long dummy1, unsigned long dummy2) >>>> { >>>> + if (!dcache_status()) >>>> + return; >>>> #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136) >>>> void arm1136_cache_flush(void); >>>> >>>> arm1136_cache_flush(); >>>> #endif >>>> #ifdef CONFIG_ARM926EJS >>>> - /* test and clean, page 2-23 of arm926ejs manual */ >>>> - asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); >>>> - /* disable write buffer as well (page 2-22) */ >>>> - asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); >>>> + /* clean& invalidate all D cache */ >>>> + asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0)); >>> >>> ARM's ARM926EJ-S r0p4/r0p5 TRM does not define "... c7, c14, 0". Where >>> did you find this exact cp15 instruction? >>> >> >> My mistake... >> Pantheon board's sheeva core modify the standard cp15 op code a bit... >> With one opcode, it could invalidate and clean the dcache all. >> >> So could I modify the original patch like below? >> asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); >> This would only invalidate all dcache. Since current dcache enable is >> just write-through, >> I think it is safe to just do the invalidate operation. >> >> This also could works for my board. > > I take my words back... > I forget to open the dcache... After dcache is on, the usb tftp still > cannot works... > Seems still do the clean cache operation... Anyway, changes to ARM926E-JS common code must work with existing ARM926E-JS SoCs, so this patch is NAK. Pantheon-specific cache ops should only be executed for Pantheon-based boards. > Best regards, > Lei Amicalement, -- Albert.