[U-Boot] PPC 405EX hangs waiting for PCIE to reset

[David Thomas <dthoma33@harris.com>]

We have a board with an AMCC PPC 405EX connected to two fpga's with PCIE 
interfaces.

On some boards, on power up, the u-boot code hangs in the while loop in 
the following code waiting for PCIE1 to come out of reset. PCIE0  comes 
out of reset successfully.

The PHYSTA for PCIE1 always reads back with the value 0x30000000, 
indicating the the interface is in the P2 state and that the PLL has not 
locked.

If a timeout is added and U-boot is allowed to proceed, a machine check 
is eventually taken and the processor reboots. During the reboot, u-boot 
runs through the same code but this time both PCIE interfaces 
successfully come out of reset and the board comes up normally.

Any suggestions about what might be happening here?

Thanks

David Thomas.



u-boot/arch/powerpc/cpu/ppc4xx/4xx_pcie.c, lines 840-848:

         SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);

     /* poll for phy !reset */
     while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
         ;

     /* deassert the PE0_gpl_utl_reset */
     SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);