From: Renaud Barbier <renaud.barbier@ge.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] P1022 eTSEC
Date: Thu, 10 Feb 2011 11:28:16 +0000 [thread overview]
Message-ID: <4D53CBD0.3000604@ge.com> (raw)
In-Reply-To: <1297288905.32737.19772.camel@petert>
I am not ready to submit a change as I have problems to boot my board on
the latest U-boot code.
I tested the change on a U-boot derived from July last year.
The tsec code is very similar to the latest code though.
Cheers,
Renaud.
On 09/02/11 22:01, Peter Tyser wrote:
> Hi Renaud,
>
> On Wed, 2011-02-09 at 20:21 +0000, Renaud Barbier wrote:
>> We have a system with a P1022 connected to a 5461S in SGMII mode.
>>
>> In order to make it work in SGMII mode, I set TBI ANA to 0x4001 as per
>> AN3869. Note that those bit are described as reserved in the P1022 doc
>> that I have.
>> I was then able to transfer data at 100/1000 (10 not tested).
>>
>> As per AN3869 a value of 0x1a0 is for 1000BASE-X.
>>
>>
>> Looking at the tsec driver (drivers/net/tsec.c), one can see:
>>
>> #define TBIANA_SETTINGS ( \
>> TBIANA_ASYMMETRIC_PAUSE \
>> | TBIANA_SYMMETRIC_PAUSE \
>> | TBIANA_FULL_DUPLEX \
>> )
>> ==> 0x1a0
>>
>> if (regs->ecntrl& ECNTRL_SGMII_MODE)
>> tsec_configure_serdes(priv);
>>
>> That would mean the TBI ANA is not set correctly when SGMII
>> is reported.
>>
>> Please can you verify this.
> Gotta love those undocumented register bits:) This same issue has been
> discussed a number of times, but no one ever noticed the 0x4001 in
> AN3869, or assumed it was an error. The bug also didn't seem to affect
> some PHYs, eg Vitesse models:
>
> http://old.nabble.com/-U-Boot---PATCH--tsec:-Force-TBI-PHY-to-1000Mbps-full-duplex-in-SGMII-mode-td26188785.html
> http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/89059
> http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/80256
>
> My company worked around the issue by not enabling auto-negotiation in
> the TBI control register via a custom CONFIG_TSEC_TBICR_SETTINGS value.
> I just tried removing our workaround and setting TBIANA_SETTINGS to
> 0x4001, and it looks like it works on a P2020-based board with a
> BCM5482S PHY.
>
> It'd be ideal if someone from from Freescale chimed in so we knew what
> bits we were hitting in the TBIANA register. The change has my ack
> though. Let me know if you don't plan on submitting a change and I'll
> update our boards, as well as the value of TBIANA_SETTINGS.
>
> Best,
> Peter
>
--
Renaud Barbier
14, Links Place
3/2 great Michael House
Edinburgh, EH67EN
Tel: +44 131 561 3532
prev parent reply other threads:[~2011-02-10 11:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-08 13:43 [U-Boot] [Nios] Pull Request Scott McNutt
2011-02-09 19:56 ` Wolfgang Denk
2011-02-09 20:21 ` [U-Boot] P1022 eTSEC Renaud Barbier
2011-02-09 20:23 ` Renaud Barbier
2011-02-09 22:01 ` Peter Tyser
2011-02-10 11:28 ` Renaud Barbier [this message]
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