From mboxrd@z Thu Jan  1 00:00:00 1970
From: Timur Tabi <timur@freescale.com>
Date: Wed, 2 Mar 2011 13:31:23 -0600
Subject: [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3
 timing_cfg_1 and sdram_mode registers
In-Reply-To: <1299091841-14594-1-git-send-email-yorksun@freescale.com>
References: <1299091841-14594-1-git-send-email-yorksun@freescale.com>
Message-ID: <4D6E9B0B.4080300@freescale.com>
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To: u-boot@lists.denx.de

York Sun wrote:
> +	switch (wrrec_mclk) { /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
> +	case 9:
> +		wrrec_mclk = 10;
> +		break;
> +	case 11:
> +		wrrec_mclk = 12;
> +		break;
> +	case 13:
> +		wrrec_mclk = 14;
> +		break;
> +	case 16:

15?

> +		wrrec_mclk = 16;
> +		break;
> +	}

How about something simpler:

if (wrrec_mclk & 1)
	wrrec_mclk++;

-- 
Timur Tabi
Linux kernel developer at Freescale