[U-Boot] [PATCH][v3] fsl_esdhc: Correcting esdhc timeout counter calculation

[Stefano Babic <sbabic@denx.de>]

On 03/03/2011 04:48 AM, Priyanka Jain wrote:
> - Timeout counter value is set as DTOCV bits in SYSCTL register
>   For counter value set as timeout,
>   Timeout period = (2^(timeout + 13)) SD Clock cycles
> 
> - As per 4.6.2.2 section of SD Card specification v2.00, host should
>   cofigure timeout period value to minimum 0.25 sec.
> 
> - Number of SD Clock cycles for 0.25sec should be minimum
> 	(SD Clock/sec * 0.25 sec) SD Clock cycles
> 	= (mmc->tran_speed * 1/4) SD Clock cycles
> 
> - Calculating timeout based on
> 	(2^(timeout + 13)) >=  mmc->tran_speed * 1/4
> 	Taking log2 both the sides and rounding up to next power of 2
> 	=> timeout + 13 = log2(mmc->tran_speed/4) + 1
> 
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> ---

Tested on a i.MX51 board.

Tested-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

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