From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Sun, 20 Mar 2011 09:18:45 +0100 Subject: [U-Boot] [PATCH 1/9] arm926ej-s: Invalidate instruction cache in flush_cache In-Reply-To: References: <1300391223-11879-1-git-send-email-mspang@csclub.uwaterloo.ca> <1300391223-11879-2-git-send-email-mspang@csclub.uwaterloo.ca> Message-ID: <4D85B865.3020305@free.fr> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Le 03/20/11 06:36, arden jay a ?crit : > Hi Michael, > > I still have question. :) > > When ARM fetch instruction, it firstly try cache. > It then should have cache miss, and forces to reload the instruction > from memory? > Why it will have problem while U-boot& Kernel at the same memory location? The error in your assumption is the "it then should have cache miss". A cache won't have a cache miss if it has already been fetched and not yet been invalidated, and the i-cache won't magically invalidate just because you do data writes at the location where the i-cache was fetched from; you end up with an i-cache that pretends to be valid but no longer matches the main memory content. Amicalement, -- Albert.