From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes
Date: Sun, 10 Apr 2011 17:30:49 +0200 [thread overview]
Message-ID: <4DA1CD29.60701@denx.de> (raw)
In-Reply-To: <1299471297-26138-1-git-send-email-galak@kernel.crashing.org>
On 03/07/2011 05:14 AM, Kumar Gala wrote:
> From: Priyanka Jain <Priyanka.Jain@freescale.com>
>
> P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
> level register description has been changed:
>
> 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
> 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
Tested on i.MX51.
Tested-by: Stefano Babic <sbabic@denx.de>
Regards,
Stefano
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next prev parent reply other threads:[~2011-04-10 15:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-07 4:14 [U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes Kumar Gala
2011-04-05 4:54 ` Kumar Gala
2011-04-10 15:30 ` Stefano Babic [this message]
2011-04-10 16:16 ` Kumar Gala
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