[U-Boot] [PATCH 6/6] EA20: do not use subpage write for NAND

Stefano Babic
2011-04-09T18:05:35Z

The NAND controller does not support subpage accessing. This is
not used at all for MLC NAND, but it is set for SLC NAND. UBI tries
to access to subpages, and because it fails, it starts "torture tests"
on the whole page that are always successful, making an endless loop
with the UBI background task taking most CPU time.
On the console, the issue is recognized by the messages:

UBI error: ubi_io_read: error -74 (ECC error) while reading 512 bytes from
PEB 37:512, read 512 bytes
UBI: run torture test for PEB 37
UBI: PEB 37 passed torture test, do not mark it a bad

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Ben Gardiner<bengardiner@nanometrics.ca>
CC: Sandeep Paulraj <s-paulraj@ti.com>
CC: Scott Wood <scottwood@freescale.com>
---
README | 4 ++++
drivers/mtd/nand/davinci_nand.c | 3 +++
include/configs/ea20.h | 1 +
include/linux/mtd/nand.h | 3 ++-
4 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/README b/README
index 21cd71b..8d664eb 100644
--- a/README
+++ b/README
@@ -2907,6 +2907,10 @@ Low Level (hardware related) configuration options:
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.

+- CONFIG_SYS_NAND_NO_SUBPAGE
+ Some drivers (davinci) do not support access to NAND subpage.
+
+
Building the Software:
======================

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c..f6c7d09 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -609,6 +609,9 @@ void davinci_nand_init(struct nand_chip *nand)
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
nand->options |= NAND_USE_FLASH_BBT;
#endif
+#ifdef CONFIG_SYS_NAND_NO_SUBPAGE
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 1843dae..9e5dda4 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -171,6 +171,7 @@

#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_NO_SUBPAGE
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#undef CONFIG_SYS_NAND_HW_ECC
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 987a2ec..215e781 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -193,7 +193,8 @@ typedef enum {
&& (chip->page_shift > 9))

/* Mask to zero out the chip options, which come from the id table */
-#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
+#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR & \
+ ~NAND_NO_SUBPAGE_WRITE)

/* Non chip related options */
/* Use a flash based bad block table. This option is passed to the
--
1.7.1