[U-Boot] [PATCH 0/3] Fix hang when loading U-Boot from SPI or NAND

[U-Boot] [PATCH 0/3] Fix hang when loading U-Boot from SPI or NAND

[Tom Warren]

This series of patches fixes a hang seen when loading U-Boot from SPI
or NAND on Seaboard and Harmony due to a missing PLLX init. It also
corrects a UARTD bit error in clk_rst.h, and adds rudimentary GPIO
support so that the UART on Seaboard can be used by U-Boot (UARTD &
SPIFLASH are muxed, and the default POR setting is for SPI access, so
GPIO_PI3 has to be driven low to enable serial console I/O over UARTD).
Harmony has no SPIFLASH, so the issue doesn't exist there.

With these changes, I can write U-Boot to SPI on Seaboard and boot with
it to the U-Boot cmd prompt. This should also apply to loading from NAND
on Seaboard and Harmony - testing to follow.

Tom Warren (3):
  arm: Tegra2: Add missing PLLX init
  arm: Tegra2: GPIO: Add basic GPIO functionality
  arm: Tegra2: Move clk/mux init to board_early_init_f, add GPIO init

 arch/arm/cpu/armv7/tegra2/ap20.c           |   29 ++++++++++++++
 arch/arm/include/asm/arch-tegra2/clk_rst.h |    6 ++-
 arch/arm/include/asm/arch-tegra2/gpio.h    |   59 ++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/tegra2.h  |    1 +
 board/nvidia/common/board.c                |   32 ++++++++++-----
 board/nvidia/common/board.h                |    4 ++
 board/nvidia/harmony/Makefile              |    1 +
 board/nvidia/harmony/harmony.c             |   34 ++++++++++++++++
 board/nvidia/seaboard/Makefile             |    1 +
 board/nvidia/seaboard/seaboard.c           |   52 ++++++++++++++++++++++++
 10 files changed, 206 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
 create mode 100644 board/nvidia/harmony/harmony.c
 create mode 100644 board/nvidia/seaboard/seaboard.c

-- 
1.7.4.3

[U-Boot] [PATCH 1/3] arm: Tegra2: Add missing PLLX init

[Tom Warren]

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/ap20.c           |   29 ++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/clk_rst.h |    6 +++-
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 075341e..ebbbbd4 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -32,6 +32,32 @@
 
 u32 s_first_boot = 1;
 
+void init_pllx(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	/* If PLLX is already enabled, just return */
+	reg = readl(&clkrst->crc_pllx_base);
+	if (reg & PLL_ENABLE)
+		return;
+
+	/* Set PLLX_MISC */
+	reg = CPCON;		/* CPCON = 0001 */
+	writel(reg, &clkrst->crc_pllx_misc);
+
+	/* Use 12MHz clock here */
+	reg = (PLL_BYPASS | PLL_DIVM);
+	reg |= (1000 << 8);			/* DIVN = 0x3E8 */
+	writel(reg, &clkrst->crc_pllx_base);
+
+	reg |= PLL_ENABLE;
+	writel(reg, &clkrst->crc_pllx_base);
+
+	reg &= ~PLL_BYPASS;
+	writel(reg, &clkrst->crc_pllx_base);
+}
+
 static void enable_cpu_clock(int enable)
 {
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
@@ -47,6 +73,9 @@ static void enable_cpu_clock(int enable)
 	 */
 
 	if (enable) {
+		/* Initialize PLLX */
+		init_pllx();
+
 		/* Wait until all clocks are stable */
 		udelay(PLL_STABILIZATION_DELAY);
 
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index d67a5d7..bd8ad2c 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -160,8 +160,8 @@ struct clk_rst_ctlr {
 #define PLL_DIVP		(1 << 20)	/* post divider, b22:20 */
 #define PLL_DIVM		0x0C		/* input divider, b4:0 */
 
-#define SWR_UARTD_RST		(1 << 2)
-#define CLK_ENB_UARTD		(1 << 2)
+#define SWR_UARTD_RST		(1 << 1)
+#define CLK_ENB_UARTD		(1 << 1)
 #define SWR_UARTA_RST		(1 << 6)
 #define CLK_ENB_UARTA		(1 << 6)
 
@@ -189,4 +189,6 @@ struct clk_rst_ctlr {
 #define CPU0_CLK_STP		(1 << 8)
 #define CPU1_CLK_STP		(1 << 9)
 
+#define CPCON			(1 << 8)
+
 #endif	/* CLK_RST_H */
-- 
1.7.4.3

[U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality

[Tom Warren]

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra2/gpio.h   |   59 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/tegra2.h |    1 +
 2 files changed, 60 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h

diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h
new file mode 100644
index 0000000..0fb8f0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_GPIO_H_
+#define _TEGRA2_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4   /* The number of ports per bank */
+#define TEGRA_GPIO_BANKS 8   /* The number of banks */
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#define GPIO_BANK(x)	((x) >> 5)
+#define GPIO_PORT(x)	(((x) >> 3) & 0x3)
+#define GPIO_BIT(x)	((x) & 0x7)
+
+/*
+ * GPIO_PI3 = Port I = 8, bit = 3.
+ * Seaboard: used for UART/SPI selection
+ * Harmony: not used
+ */
+#define GPIO_PI3	((8 << 3) | 3)
+
+#endif	/* TEGRA2_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 7b0f5cc..742a75a 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -30,6 +30,7 @@
 #define NV_PA_TMRUS_BASE	0x60005010
 #define NV_PA_CLK_RST_BASE	0x60006000
 #define NV_PA_FLOW_BASE		0x60007000
+#define NV_PA_GPIO_BASE		0x6000D000
 #define NV_PA_EVP_BASE		0x6000F000
 #define NV_PA_APB_MISC_BASE	0x70000000
 #define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
-- 
1.7.4.3

[U-Boot] [PATCH 3/3] arm: Tegra2: Move clk/mux init to board_early_init_f, add GPIO init

[Tom Warren]

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/common/board.c      |   32 +++++++++++++++--------
 board/nvidia/common/board.h      |    4 +++
 board/nvidia/harmony/Makefile    |    1 +
 board/nvidia/harmony/harmony.c   |   34 ++++++++++++++++++++++++
 board/nvidia/seaboard/Makefile   |    1 +
 board/nvidia/seaboard/seaboard.c |   52 ++++++++++++++++++++++++++++++++++++++
 6 files changed, 113 insertions(+), 11 deletions(-)
 create mode 100644 board/nvidia/harmony/harmony.c
 create mode 100644 board/nvidia/seaboard/seaboard.c

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 5edd70f..3d6c248 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -41,7 +41,16 @@ const struct tegra2_sysinfo sysinfo = {
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	debug("Board Early Init\n");
+	/* Initialize periph clocks */
+	clock_init();
+
+	/* Initialize periph pinmuxes */
+	pinmux_init();
+
+	/* Initialize periph GPIOs */
+	gpio_init();
+
+	/* Init UART, scratch regs, and start CPU */
 	tegra2_start();
 	return 0;
 }
@@ -64,10 +73,10 @@ int timer_init(void)
 static void clock_init_uart(void)
 {
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	static int pllp_init_done;
 	u32 reg;
 
-	if (!pllp_init_done) {
+	reg = readl(&clkrst->crc_pllp_base);
+	if (!(reg & PLL_BASE_OVRRIDE)) {
 		/* Override pllp setup for 216MHz operation. */
 		reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
 		reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
@@ -78,8 +87,6 @@ static void clock_init_uart(void)
 
 		reg &= ~PLL_BYPASS;
 		writel(reg, &clkrst->crc_pllp_base);
-
-		pllp_init_done++;
 	}
 
 	/* Now do the UART reset/clock enable */
@@ -182,6 +189,15 @@ void pinmux_init(void)
 }
 
 /*
+ * Routine: gpio_init
+ * Description: Do individual peripheral GPIO configs
+ */
+void gpio_init(void)
+{
+	gpio_config_uart();
+}
+
+/*
  * Routine: board_init
  * Description: Early hardware init.
  */
@@ -192,11 +208,5 @@ int board_init(void)
 	/* board id for Linux */
 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 
-	/* Initialize peripheral clocks */
-	clock_init();
-
-	/* Initialize periph pinmuxes */
-	pinmux_init();
-
 	return 0;
 }
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index 47c7885..350bc57 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -25,5 +25,9 @@
 #define _BOARD_H_
 
 void tegra2_start(void);
+void clock_init(void);
+void pinmux_init(void);
+void gpio_init(void);
+void gpio_config_uart(void);
 
 #endif	/* BOARD_H */
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
index 3a146cb..9fb6b57 100644
--- a/board/nvidia/harmony/Makefile
+++ b/board/nvidia/harmony/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+COBJS	:= $(BOARD).o
 COBJS	+= ../common/board.o
 
 SRCS	:= $(COBJS:.o=.c)
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
new file mode 100644
index 0000000..f1ab050
--- /dev/null
+++ b/board/nvidia/harmony/harmony.c
@@ -0,0 +1,34 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Harmony - no conflict w/SPI.
+ */
+void gpio_config_uart(void)
+{
+}
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
index 3a146cb..9fb6b57 100644
--- a/board/nvidia/seaboard/Makefile
+++ b/board/nvidia/seaboard/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+COBJS	:= $(BOARD).o
 COBJS	+= ../common/board.o
 
 SRCS	:= $(COBJS:.o=.c)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
new file mode 100644
index 0000000..4b9a8f3
--- /dev/null
+++ b/board/nvidia/seaboard/seaboard.c
@@ -0,0 +1,52 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Force GPIO_PI3 low on Seaboard so UART4 works.
+ */
+void gpio_config_uart(void)
+{
+	int gp = GPIO_PI3;
+	struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)];
+	u32 val;
+
+	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
+	val = readl(&bank->gpio_config[GPIO_PORT(gp)]);
+	val |= 1 << GPIO_BIT(gp);
+	writel(val, &bank->gpio_config[GPIO_PORT(gp)]);
+
+	val = readl(&bank->gpio_out[GPIO_PORT(gp)]);
+	val &= ~(1 << GPIO_BIT(gp));
+	writel(val, &bank->gpio_out[GPIO_PORT(gp)]);
+
+	val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]);
+	val |= 1 << GPIO_BIT(gp);
+	writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]);
+}
-- 
1.7.4.3

[U-Boot] [PATCH 1/3] arm: Tegra2: Add missing PLLX init

[Albert ARIBAUD]

Le 13/04/2011 22:07, Tom Warren a ?crit :

> +	reg = CPCON;		/* CPCON = 0001 */

> +#define CPCON			(1<<  8)

Which one is the correct value? 0001 or 0x100?

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality

[Albert ARIBAUD]

Hi Tom,

Le 13/04/2011 22:07, Tom Warren a ?crit :
> Signed-off-by: Tom Warren<twarren@nvidia.com>
> ---
>   arch/arm/include/asm/arch-tegra2/gpio.h   |   59 +++++++++++++++++++++++++++++
>   arch/arm/include/asm/arch-tegra2/tegra2.h |    1 +
>   2 files changed, 60 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
>
> diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h
> new file mode 100644
> index 0000000..0fb8f0d
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-tegra2/gpio.h
> @@ -0,0 +1,59 @@
> +/*
> + * Copyright (c) 2011, Google Inc. All rights reserved.
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _TEGRA2_GPIO_H_
> +#define _TEGRA2_GPIO_H_
> +
> +/*
> + * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports,
> + * each with 8 GPIOs.
> + */
> +#define TEGRA_GPIO_PORTS 4   /* The number of ports per bank */
> +#define TEGRA_GPIO_BANKS 8   /* The number of banks */
> +
> +/* GPIO Controller registers for a single bank */
> +struct gpio_ctlr_bank {
> +	uint gpio_config[TEGRA_GPIO_PORTS];
> +	uint gpio_dir_out[TEGRA_GPIO_PORTS];
> +	uint gpio_out[TEGRA_GPIO_PORTS];
> +	uint gpio_in[TEGRA_GPIO_PORTS];
> +	uint gpio_int_status[TEGRA_GPIO_PORTS];
> +	uint gpio_int_enable[TEGRA_GPIO_PORTS];
> +	uint gpio_int_level[TEGRA_GPIO_PORTS];
> +	uint gpio_int_clear[TEGRA_GPIO_PORTS];
> +};
> +
> +struct gpio_ctlr {
> +	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
> +};
> +
> +#define GPIO_BANK(x)	((x)>>  5)
> +#define GPIO_PORT(x)	(((x)>>  3)&  0x3)
> +#define GPIO_BIT(x)	((x)&  0x7)
> +
> +/*
> + * GPIO_PI3 = Port I = 8, bit = 3.
> + * Seaboard: used for UART/SPI selection
> + * Harmony: not used
> + */
> +#define GPIO_PI3	((8<<  3) | 3)
> +
> +#endif	/* TEGRA2_GPIO_H_ */
> diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
> index 7b0f5cc..742a75a 100644
> --- a/arch/arm/include/asm/arch-tegra2/tegra2.h
> +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
> @@ -30,6 +30,7 @@
>   #define NV_PA_TMRUS_BASE	0x60005010
>   #define NV_PA_CLK_RST_BASE	0x60006000
>   #define NV_PA_FLOW_BASE		0x60007000
> +#define NV_PA_GPIO_BASE		0x6000D000
>   #define NV_PA_EVP_BASE		0x6000F000
>   #define NV_PA_APB_MISC_BASE	0x70000000
>   #define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)

These are header files only, and they do not even contain function-like 
macros, so where is the functionality exactly?

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 1/3] arm: Tegra2: Add missing PLLX init

[Tom Warren]

CPCON (Charge Pump Control) is a 4-bit field, bits 11:8. The default
value is 0001. I'll change the comment to /* CPCON [11:8] = 0001 */

On Wed, Apr 13, 2011 at 1:12 PM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Le 13/04/2011 22:07, Tom Warren a ?crit :
>
>> + ? ? ? reg = CPCON; ? ? ? ? ? ?/* CPCON = 0001 */
>
>> +#define CPCON ? ? ? ? ? ? ? ? ?(1<< ?8)
>
> Which one is the correct value? 0001 or 0x100?
>
> Amicalement,
> --
> Albert.
>

[U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality

[Tom Warren]

Albert,

On Wed, Apr 13, 2011 at 1:14 PM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Hi Tom,
>
> Le 13/04/2011 22:07, Tom Warren a ?crit :
>>
>> Signed-off-by: Tom Warren<twarren@nvidia.com>
>> ---
>> ?arch/arm/include/asm/arch-tegra2/gpio.h ? | ? 59
>> +++++++++++++++++++++++++++++
>> ?arch/arm/include/asm/arch-tegra2/tegra2.h | ? ?1 +
>> ?2 files changed, 60 insertions(+), 0 deletions(-)
>> ?create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
>>
>> diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
>> b/arch/arm/include/asm/arch-tegra2/gpio.h
>> new file mode 100644
>> index 0000000..0fb8f0d
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-tegra2/gpio.h
>> @@ -0,0 +1,59 @@
>> +/*
>> + * Copyright (c) 2011, Google Inc. All rights reserved.
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#ifndef _TEGRA2_GPIO_H_
>> +#define _TEGRA2_GPIO_H_
>> +
>> +/*
>> + * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4
>> ports,
>> + * each with 8 GPIOs.
>> + */
>> +#define TEGRA_GPIO_PORTS 4 ? /* The number of ports per bank */
>> +#define TEGRA_GPIO_BANKS 8 ? /* The number of banks */
>> +
>> +/* GPIO Controller registers for a single bank */
>> +struct gpio_ctlr_bank {
>> + ? ? ? uint gpio_config[TEGRA_GPIO_PORTS];
>> + ? ? ? uint gpio_dir_out[TEGRA_GPIO_PORTS];
>> + ? ? ? uint gpio_out[TEGRA_GPIO_PORTS];
>> + ? ? ? uint gpio_in[TEGRA_GPIO_PORTS];
>> + ? ? ? uint gpio_int_status[TEGRA_GPIO_PORTS];
>> + ? ? ? uint gpio_int_enable[TEGRA_GPIO_PORTS];
>> + ? ? ? uint gpio_int_level[TEGRA_GPIO_PORTS];
>> + ? ? ? uint gpio_int_clear[TEGRA_GPIO_PORTS];
>> +};
>> +
>> +struct gpio_ctlr {
>> + ? ? ? struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
>> +};
>> +
>> +#define GPIO_BANK(x) ? ((x)>> ?5)
>> +#define GPIO_PORT(x) ? (((x)>> ?3)& ?0x3)
>> +#define GPIO_BIT(x) ? ?((x)& ?0x7)
>> +
>> +/*
>> + * GPIO_PI3 = Port I = 8, bit = 3.
>> + * Seaboard: used for UART/SPI selection
>> + * Harmony: not used
>> + */
>> +#define GPIO_PI3 ? ? ? ((8<< ?3) | 3)
>> +
>> +#endif /* TEGRA2_GPIO_H_ */
>> diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h
>> b/arch/arm/include/asm/arch-tegra2/tegra2.h
>> index 7b0f5cc..742a75a 100644
>> --- a/arch/arm/include/asm/arch-tegra2/tegra2.h
>> +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
>> @@ -30,6 +30,7 @@
>> ?#define NV_PA_TMRUS_BASE ? ? ?0x60005010
>> ?#define NV_PA_CLK_RST_BASE ? ?0x60006000
>> ?#define NV_PA_FLOW_BASE ? ? ? ? ? ? ? 0x60007000
>> +#define NV_PA_GPIO_BASE ? ? ? ? ? ? ? ?0x6000D000
>> ?#define NV_PA_EVP_BASE ? ? ? ? ? ? ? ?0x6000F000
>> ?#define NV_PA_APB_MISC_BASE ? 0x70000000
>> ?#define NV_PA_APB_UARTA_BASE ?(NV_PA_APB_MISC_BASE + 0x6000)
>
> These are header files only, and they do not even contain function-like
> macros, so where is the functionality exactly?
In the next patch (3/3) - the macros are used in seaboard.c to drive
the UART_DISABLE GPIO low to enable the UART in U-Boot POST.

>
> Amicalement,
> --
> Albert.
>

Tom

[U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality

[Albert ARIBAUD]

Tom,

Le 13/04/2011 22:26, Tom Warren a ?crit :
> Albert,
>
> On Wed, Apr 13, 2011 at 1:14 PM, Albert ARIBAUD
> <albert.u.boot@aribaud.net>  wrote:
>> Hi Tom,
>>
>> Le 13/04/2011 22:07, Tom Warren a ?crit :
>>>
>>> Signed-off-by: Tom Warren<twarren@nvidia.com>
>>> ---
>>>   arch/arm/include/asm/arch-tegra2/gpio.h   |   59
>>> +++++++++++++++++++++++++++++
>>>   arch/arm/include/asm/arch-tegra2/tegra2.h |    1 +
>>>   2 files changed, 60 insertions(+), 0 deletions(-)
>>>   create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
>>>
>>> diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
>>> b/arch/arm/include/asm/arch-tegra2/gpio.h
>>> new file mode 100644
>>> index 0000000..0fb8f0d
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-tegra2/gpio.h
>>> @@ -0,0 +1,59 @@
>>> +/*
>>> + * Copyright (c) 2011, Google Inc. All rights reserved.
>>> + * See file CREDITS for list of people who contributed to this
>>> + * project.
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of
>>> + * the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>> + * MA 02111-1307 USA
>>> + */
>>> +
>>> +#ifndef _TEGRA2_GPIO_H_
>>> +#define _TEGRA2_GPIO_H_
>>> +
>>> +/*
>>> + * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4
>>> ports,
>>> + * each with 8 GPIOs.
>>> + */
>>> +#define TEGRA_GPIO_PORTS 4   /* The number of ports per bank */
>>> +#define TEGRA_GPIO_BANKS 8   /* The number of banks */
>>> +
>>> +/* GPIO Controller registers for a single bank */
>>> +struct gpio_ctlr_bank {
>>> +       uint gpio_config[TEGRA_GPIO_PORTS];
>>> +       uint gpio_dir_out[TEGRA_GPIO_PORTS];
>>> +       uint gpio_out[TEGRA_GPIO_PORTS];
>>> +       uint gpio_in[TEGRA_GPIO_PORTS];
>>> +       uint gpio_int_status[TEGRA_GPIO_PORTS];
>>> +       uint gpio_int_enable[TEGRA_GPIO_PORTS];
>>> +       uint gpio_int_level[TEGRA_GPIO_PORTS];
>>> +       uint gpio_int_clear[TEGRA_GPIO_PORTS];
>>> +};
>>> +
>>> +struct gpio_ctlr {
>>> +       struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
>>> +};
>>> +
>>> +#define GPIO_BANK(x)   ((x)>>    5)
>>> +#define GPIO_PORT(x)   (((x)>>    3)&    0x3)
>>> +#define GPIO_BIT(x)    ((x)&    0x7)
>>> +
>>> +/*
>>> + * GPIO_PI3 = Port I = 8, bit = 3.
>>> + * Seaboard: used for UART/SPI selection
>>> + * Harmony: not used
>>> + */
>>> +#define GPIO_PI3       ((8<<    3) | 3)
>>> +
>>> +#endif /* TEGRA2_GPIO_H_ */
>>> diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h
>>> b/arch/arm/include/asm/arch-tegra2/tegra2.h
>>> index 7b0f5cc..742a75a 100644
>>> --- a/arch/arm/include/asm/arch-tegra2/tegra2.h
>>> +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
>>> @@ -30,6 +30,7 @@
>>>   #define NV_PA_TMRUS_BASE      0x60005010
>>>   #define NV_PA_CLK_RST_BASE    0x60006000
>>>   #define NV_PA_FLOW_BASE               0x60007000
>>> +#define NV_PA_GPIO_BASE                0x6000D000
>>>   #define NV_PA_EVP_BASE                0x6000F000
>>>   #define NV_PA_APB_MISC_BASE   0x70000000
>>>   #define NV_PA_APB_UARTA_BASE  (NV_PA_APB_MISC_BASE + 0x6000)
>>
>> These are header files only, and they do not even contain function-like
>> macros, so where is the functionality exactly?
> In the next patch (3/3) - the macros are used in seaboard.c to drive
> the UART_DISABLE GPIO low to enable the UART in U-Boot POST.

Could you just rename the patch "Add basic GPIO definitions" then?

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 2/3] arm: Tegra2: GPIO: Add basic GPIO functionality

[Tom Warren]

Albert,

On Wed, Apr 13, 2011 at 1:31 PM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Tom,
>
> Le 13/04/2011 22:26, Tom Warren a ?crit :
>>
>> Albert,
>>
>> On Wed, Apr 13, 2011 at 1:14 PM, Albert ARIBAUD
>> <albert.u.boot@aribaud.net> ?wrote:
>>>
>>> Hi Tom,
>>>
>>> Le 13/04/2011 22:07, Tom Warren a ?crit :
>>>>
>>>> Signed-off-by: Tom Warren<twarren@nvidia.com>
>>>> ---
>>>> ?arch/arm/include/asm/arch-tegra2/gpio.h ? | ? 59
>>>> +++++++++++++++++++++++++++++
>>>> ?arch/arm/include/asm/arch-tegra2/tegra2.h | ? ?1 +
>>>> ?2 files changed, 60 insertions(+), 0 deletions(-)
>>>> ?create mode 100644 arch/arm/include/asm/arch-tegra2/gpio.h
>>>>
>>>> diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h
>>>> b/arch/arm/include/asm/arch-tegra2/gpio.h
>>>> new file mode 100644
>>>> index 0000000..0fb8f0d
>>>> --- /dev/null
>>>> +++ b/arch/arm/include/asm/arch-tegra2/gpio.h
>>>> @@ -0,0 +1,59 @@
>>>> +/*
>>>> + * Copyright (c) 2011, Google Inc. All rights reserved.
>>>> + * See file CREDITS for list of people who contributed to this
>>>> + * project.
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> + * modify it under the terms of the GNU General Public License as
>>>> + * published by the Free Software Foundation; either version 2 of
>>>> + * the License, or (at your option) any later version.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>>>> + * GNU General Public License for more details.
>>>> + *
>>>> + * You should have received a copy of the GNU General Public License
>>>> + * along with this program; if not, write to the Free Software
>>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>>> + * MA 02111-1307 USA
>>>> + */
>>>> +
>>>> +#ifndef _TEGRA2_GPIO_H_
>>>> +#define _TEGRA2_GPIO_H_
>>>> +
>>>> +/*
>>>> + * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4
>>>> ports,
>>>> + * each with 8 GPIOs.
>>>> + */
>>>> +#define TEGRA_GPIO_PORTS 4 ? /* The number of ports per bank */
>>>> +#define TEGRA_GPIO_BANKS 8 ? /* The number of banks */
>>>> +
>>>> +/* GPIO Controller registers for a single bank */
>>>> +struct gpio_ctlr_bank {
>>>> + ? ? ? uint gpio_config[TEGRA_GPIO_PORTS];
>>>> + ? ? ? uint gpio_dir_out[TEGRA_GPIO_PORTS];
>>>> + ? ? ? uint gpio_out[TEGRA_GPIO_PORTS];
>>>> + ? ? ? uint gpio_in[TEGRA_GPIO_PORTS];
>>>> + ? ? ? uint gpio_int_status[TEGRA_GPIO_PORTS];
>>>> + ? ? ? uint gpio_int_enable[TEGRA_GPIO_PORTS];
>>>> + ? ? ? uint gpio_int_level[TEGRA_GPIO_PORTS];
>>>> + ? ? ? uint gpio_int_clear[TEGRA_GPIO_PORTS];
>>>> +};
>>>> +
>>>> +struct gpio_ctlr {
>>>> + ? ? ? struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
>>>> +};
>>>> +
>>>> +#define GPIO_BANK(x) ? ((x)>> ? ?5)
>>>> +#define GPIO_PORT(x) ? (((x)>> ? ?3)& ? ?0x3)
>>>> +#define GPIO_BIT(x) ? ?((x)& ? ?0x7)
>>>> +
>>>> +/*
>>>> + * GPIO_PI3 = Port I = 8, bit = 3.
>>>> + * Seaboard: used for UART/SPI selection
>>>> + * Harmony: not used
>>>> + */
>>>> +#define GPIO_PI3 ? ? ? ((8<< ? ?3) | 3)
>>>> +
>>>> +#endif /* TEGRA2_GPIO_H_ */
>>>> diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h
>>>> b/arch/arm/include/asm/arch-tegra2/tegra2.h
>>>> index 7b0f5cc..742a75a 100644
>>>> --- a/arch/arm/include/asm/arch-tegra2/tegra2.h
>>>> +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
>>>> @@ -30,6 +30,7 @@
>>>> ?#define NV_PA_TMRUS_BASE ? ? ?0x60005010
>>>> ?#define NV_PA_CLK_RST_BASE ? ?0x60006000
>>>> ?#define NV_PA_FLOW_BASE ? ? ? ? ? ? ? 0x60007000
>>>> +#define NV_PA_GPIO_BASE ? ? ? ? ? ? ? ?0x6000D000
>>>> ?#define NV_PA_EVP_BASE ? ? ? ? ? ? ? ?0x6000F000
>>>> ?#define NV_PA_APB_MISC_BASE ? 0x70000000
>>>> ?#define NV_PA_APB_UARTA_BASE ?(NV_PA_APB_MISC_BASE + 0x6000)
>>>
>>> These are header files only, and they do not even contain function-like
>>> macros, so where is the functionality exactly?
>>
>> In the next patch (3/3) - the macros are used in seaboard.c to drive
>> the UART_DISABLE GPIO low to enable the UART in U-Boot POST.
>
> Could you just rename the patch "Add basic GPIO definitions" then?
Sure, no problem. Thanks.

>
> Amicalement,
> --
> Albert.
>