[U-Boot] [PATCH 29/30] arm/km: change default settings for egiga on mgcoge3un

Valentin Longchamp
2011-04-08T14:24:19Z

From: Holger Brunck <holger.brunck@keymile.com>

The reason we need this is that we have the gig port on mgcoge3un
connected using a back-to-back pair of PHYs. There are no magnetics and
because of that the port has to be run with a fixd configuration and
auto-negotiation must be disabled. In the default mode the egiga driver
uses autoneg to determine port speed - which defaults to 1G (we need
100M full duplex).

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <wd@denx.de>
cc: Detlev Zundel <dzu@denx.de>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
drivers/net/mvgbe.h | 2 ++
include/configs/mgcoge3un.h | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index 3de98d0..d8a5429 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -84,6 +84,7 @@
MVGBE_TX_BURST_SIZE_16_64BIT)

/* Default port serial control value */
+#ifndef PORT_SERIAL_CONTROL_VALUE
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
@@ -101,6 +102,7 @@
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+#endif

/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h
index da5935b..c7f9056 100644
--- a/include/configs/mgcoge3un.h
+++ b/include/configs/mgcoge3un.h
@@ -48,6 +48,31 @@
#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/

/*
+ * mgcoge3un has a fixed link to the marvell switch
+ * with 100MB full duplex and autoneg off, for this
+ * reason we have to change the default settings
+ */
+#define PORT_SERIAL_CONTROL_VALUE ( \
+ MVGBE_FORCE_LINK_PASS | \
+ MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
+ MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ MVGBE_ADV_NO_FLOW_CTRL | \
+ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ MVGBE_FORCE_BP_MODE_NO_JAM | \
+ (1 << 9) /* Reserved bit has to be 1 */ | \
+ MVGBE_DO_NOT_FORCE_LINK_FAIL | \
+ MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
+ MVGBE_DTE_ADV_0 | \
+ MVGBE_MIIPHY_MAC_MODE | \
+ MVGBE_AUTO_NEG_NO_CHANGE | \
+ MVGBE_MAX_RX_PACKET_1552BYTE | \
+ MVGBE_CLR_EXT_LOOPBACK | \
+ MVGBE_SET_FULL_DUPLEX_MODE | \
+ MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
+ MVGBE_SET_GMII_SPEED_TO_10_100 |\
+ MVGBE_SET_MII_SPEED_TO_100)
+
+/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
--
1.7.0.5