From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Tue, 17 May 2011 15:10:17 +0200 Subject: [U-Boot] [PATCH v2 3/3] MX53: Add initial support for MX53ARD board In-Reply-To: <1305584991-13040-3-git-send-email-fabio.estevam@freescale.com> References: <1305584991-13040-1-git-send-email-fabio.estevam@freescale.com> <1305584991-13040-2-git-send-email-fabio.estevam@freescale.com> <1305584991-13040-3-git-send-email-fabio.estevam@freescale.com> Message-ID: <4DD273B9.80209@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/17/2011 12:29 AM, Fabio Estevam wrote: > Signed-off-by: Fabio Estevam Hi Fabio, > +#define ETHERNET_INT (1*32 + 31) /* GPIO2_31 */ ^-- missing space If you want to write in this form, it should be "1 * 32 + 31". > +void weim_cs1_settings() > +{ > + unsigned int reg; > + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; > + struct iomuxc *iomuxc_regs = (struct weim *)IOMUXC_BASE_ADDR; > + > + writel(0x00020001, &weim_regs->cs1gcr1); > + writel(0x00000000, &weim_regs->cs1gcr2); > + writel(0x16000202, &weim_regs->cs1rcr1); > + writel(0x00000002, &weim_regs->cs1rcr2); > + writel(0x16002082, &weim_regs->cs1wcr1); > + writel(0x00000000, &weim_regs->cs1wcr2); > + writel(0x00000000, &weim_regs->wcr); Can you add #defines to describe the weim registers ? Thius is helpful for MX51, too. > + > + /* specify 64 MB on CS1 and CS0 */ > + reg = readl(&iomuxc_regs->gpr1); > + reg &= ~0x3F; > + reg |= 0x1B; A macro to set the single chip select is better, something as CS_SET_SIZE(chipselect, size), or something like that. What do you think about it ? Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================