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From: Aneesh V <aneesh@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 02/10] armv7: add miscellaneous utility macros
Date: Wed, 08 Jun 2011 17:23:10 +0530	[thread overview]
Message-ID: <4DEF62A6.7060706@ti.com> (raw)
In-Reply-To: <20110607154028.D6540195494F@gemini.denx.de>

Dear Wolfgang,

On Tuesday 07 June 2011 09:10 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DEE161B.2050402@ti.com>  you wrote:
>>
>>>> So, if I have to write 5 different fields in a register I first write
>>>> them into a variable and finally call writel() instead of making 5
>>>> clrsetbits*() calls.
>>>
>>> It does not make much difference to me if you call one macro or
>>> another 5 times.
>>
>> No it makes a difference. It's 5 writes to a variable typically in an
>> ARM register + 1 IO access vs 5 IO accesses. It's logically not
>> equivalent.
>
> You can use in_le32() to read the register in a variable, a number of
> macros operating on that variable, and then a out_le32() to write it
> back.
>
> It's logically equivalent.
>
>> Further if the 5 values are constants a smart compiler will fold the
>> five writes into one write to the ARM register + 1 IO access, which
>> won't happen if you used 5 clrsetbits*()
>
> See above.
>
> If you ever want to use your macros on device registers, you MUST use
> proper memory barriers.  This will probably ruin your idea to combine
> the access into a single write.  So you can just work on a variable as
> suggested before.
>
>> Problem: We want to read-modify-write an IO register 'reg' affecting 3
>> different fields: a, b, and c. The values to be written to the fields
>> are a_val, b_val, and c_val respectively:
>>
>> Solution 1 - without any macros:
>>
>> unsigned int r = readl(reg);
>> r = (r&  ~a_mask) | ((a_val<<  a_shift)&  a_mask)
>> r = (r&  ~b_mask) | ((b_val<<  b_shift)&  b_mask)
>> r = (r&  ~c_mask) | ((c_val<<  c_shift)&  c_mask)
>> writel(r, reg);
>>
>> Solution2 - with my macros:
>>
>> unsigned int r = readl(reg);
>> set_bit_field(r, a, a_val);
>> set_bit_field(r, b, b_val);
>> set_bit_field(r, c, c_val);
>> writel(r, reg);
>>
>> Solution3 - with clrsetbits*():
>>
>> clrsetbits_le32(reg, a_mask, a_val<<  a_shift);
>> clrsetbits_le32(reg, b_mask, b_val<<  b_shift);
>> clrsetbits_le32(reg, c_mask, c_val<<  c_shift);
>
> Solution 4 - with standard macros, and proper defines:
>
> 	unsigned int r = in_le32(reg);		/* or readl() if you like */
>
> 	clrsetbits_le32(&r, a_mask, a_val);
> 	clrsetbits_le32(&r, b_mask, b_val);
> 	clrsetbits_le32(&r, c_mask, c_val);
>
> 	out_le32(reg, r);

I still don't think this is the 'right' solution for my problem. I don't
like the fact that clrsetbits_le32() introduces a lot of un-necessary
'volatile's.

Yes, it's about the 'efficiency'. May be it doesn't count in some
cases. But, may be it counts in some other cases. Basically, I don't
like to sacrifice 'efficiency' unless the cost for achieving it is very
high. I don't think having an extra helper function is a big cost.
Neither do I believe that readability suffers in this case.

If you still insist, I can use clrsetbits_le32() in the interest
of getting this to a closure.

>
> Actually solution 3 looks best to me.
>
>> Solution 3 is not acceptable to me because it's clearly not equivalent
>> to what I want to do. Writing the register 3 times instead of once may
>> have undesirable side-effects. Even if it worked, it's clearly not
>> efficient.
>
> In case of side effects you can use solution 4.
>
> We should not bother here about wether this is "efficient" or "not
> efficient".  Probably none opf this code is ever time critical, not to
> the extent of a few additional instructions.
>
>> If you are forcing me to use solution 1, IMHO you are essentially
>> forcing me not to use a sub-routine for a task that is repeated many
>> times in my code, leaving my code to be more error prone and less
>> readable.
>
> I agree that 1 is ugly and error prone, but there is no need to use
> it.
>
> I repeat:  we have a set of powerful macros ready available.  Just use
> them.

We have a set of powerful macros designed for bit-field accesses in IO
egisters.

But, what I am looking for is a set of macros for bit-field operations
on C integer variables without the un-necessary overhead of IO register
accesses. I am looking for missing APIs in bitops.h not anything from
io.h

best regards,
Aneesh

  reply	other threads:[~2011-06-08 11:53 UTC|newest]

Thread overview: 105+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-08 13:07 [U-Boot] [PATCH v2 00/10] armv7: cache maintenance operations Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 01/10] arm: make default implementation of cache_flush() weakly linked Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 02/10] armv7: add miscellaneous utility macros Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 03/10] armv7: cache maintenance operations for armv7 Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 04/10] armv7: replace CONFIG_L2_OFF with CONFIG_SYS_NO_L2CACHE Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 05/10] armv7: integrate cache maintenance support Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 06/10] arm: minor fixes for cache and mmu handling Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 07/10] armv7: add PL310 support to u-boot Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 08/10] armv7: adapt omap4 to the new cache maintenance framework Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 09/10] armv7: adapt omap3 " Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 10/10] armv7: adapt s5pc1xx " Aneesh V
2011-04-27  1:05 ` [U-Boot] [PATCH v2 00/10] armv7: cache maintenance operations Simon Glass
2011-05-05  4:48   ` Simon Glass
2011-05-10 10:25     ` Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 " Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 01/10] arm: make default implementation of cache_flush() weakly linked Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 02/10] armv7: add miscellaneous utility macros Aneesh V
2011-05-15 18:44   ` Wolfgang Denk
2011-05-15 22:15     ` Simon Glass
2011-05-16  2:23       ` Eric Cooper
2011-05-16 14:50         ` Simon Glass
2011-05-16 15:52           ` Wolfgang Denk
2011-05-16  5:51       ` Wolfgang Denk
2011-05-17  3:47         ` Simon Glass
2011-05-17  5:27           ` Wolfgang Denk
2011-05-17  8:44             ` Aneesh V
2011-05-17  9:27               ` Wolfgang Denk
2011-05-31  7:54                 ` V, Aneesh
2011-06-01  2:13                   ` Simon Glass
2011-06-01  6:01                     ` Aneesh V
2011-05-16 15:07     ` Aneesh V
2011-06-06 15:57       ` Aneesh V
2011-06-06 18:50         ` Wolfgang Denk
2011-06-07  9:01           ` Aneesh V
2011-06-07 10:39             ` Wolfgang Denk
2011-06-07 12:14               ` Aneesh V
2011-06-07 15:19                 ` Simon Glass
2011-06-07 15:40                 ` Wolfgang Denk
2011-06-08 11:53                   ` Aneesh V [this message]
2011-06-08 21:41                     ` Wolfgang Denk
2011-06-14  8:45                       ` Aneesh V
2011-06-14 10:51                         ` Wolfgang Denk
2011-06-14 11:39                           ` Aneesh V
2011-06-14 13:53                             ` Wolfgang Denk
2011-06-14 15:11                               ` Simon Glass
2011-06-14 18:54                                 ` Wolfgang Denk
2011-06-15 15:19                                   ` Simon Glass
2011-06-15  8:48                               ` Aneesh V
2011-06-15  9:20                                 ` Wolfgang Denk
2011-06-15 11:01                                   ` Aneesh V
2011-06-15 12:04                                     ` Wolfgang Denk
2011-06-15 12:42                                       ` Graeme Russ
2011-06-15 12:51                                         ` Wolfgang Denk
2011-06-15 13:03                                           ` Graeme Russ
2011-06-16 11:07                                           ` Graeme Russ
2011-06-16 11:46                                             ` Wolfgang Denk
2011-06-16 23:58                                               ` Graeme Russ
2011-06-16  5:39                                         ` Aneesh V
2011-06-16  6:19                                           ` Graeme Russ
2011-06-16  8:15                                             ` Wolfgang Denk
2011-06-16 11:10                                               ` Graeme Russ
2011-05-12 12:11 ` [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7 Aneesh V
2011-05-15 18:51   ` Wolfgang Denk
2011-05-17  9:17     ` Aneesh V
2011-05-17  9:31       ` Wolfgang Denk
2011-05-17  9:37         ` Aneesh V
2011-05-17  9:58         ` Aneesh V
2011-06-16 14:17           ` Simon Glass
2011-05-12 12:11 ` [U-Boot] [PATCH v3 04/10] armv7: replace CONFIG_L2_OFF with CONFIG_SYS_NO_L2CACHE Aneesh V
2011-05-15 18:53   ` Wolfgang Denk
2011-05-17  9:59     ` Aneesh V
2011-05-17 11:09       ` Wolfgang Denk
2011-06-06 11:39         ` Aneesh V
2011-06-15 10:13           ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 05/10] armv7: integrate cache maintenance support Aneesh V
2011-05-15 18:55   ` Wolfgang Denk
2011-05-17 10:20     ` Aneesh V
2011-05-17 11:14       ` Wolfgang Denk
2011-05-17 12:06         ` Aneesh V
2011-05-17 12:28           ` Wolfgang Denk
2011-05-17 13:28             ` Aneesh V
2011-05-17 21:37               ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 06/10] arm: minor fixes for cache and mmu handling Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 07/10] armv7: add PL310 support to u-boot Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 08/10] armv7: adapt omap4 to the new cache maintenance framework Aneesh V
2011-05-15 18:57   ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 09/10] armv7: adapt omap3 " Aneesh V
2011-05-15 18:58   ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 10/10] armv7: adapt s5pc1xx " Aneesh V
2011-05-15 18:59   ` Wolfgang Denk
2011-06-17  9:30 ` [U-Boot] [PATCH v4 0/9] armv7: cache maintenance operations Aneesh V
2011-06-22 17:41   ` Albert ARIBAUD
2011-06-23  5:57     ` V, Aneesh
2011-06-23 19:24     ` Paulraj, Sandeep
2011-06-28  1:44       ` Minkyu Kang
2011-06-28  5:41   ` Albert ARIBAUD
2011-06-17  9:30 ` [U-Boot] [PATCH v4 1/9] arm: make default implementation of cache_flush() weakly linked Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 2/9] armv7: cache maintenance operations for armv7 Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 3/9] armv7: rename cache related CONFIG flags Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 4/9] armv7: integrate cache maintenance support Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 5/9] arm: minor fixes for cache and mmu handling Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 6/9] armv7: add PL310 support to u-boot Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 7/9] armv7: adapt omap4 to the new cache maintenance framework Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 8/9] armv7: adapt omap3 " Aneesh V
2011-06-17  9:30 ` [U-Boot] [PATCH v4 9/9] armv7: adapt s5pc1xx " Aneesh V

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