From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aneesh V Date: Thu, 30 Jun 2011 16:08:16 +0530 Subject: [U-Boot] [2/5]devkit8000 nand_spl: omap3 support nand_spl boot In-Reply-To: <1309270480-31918-3-git-send-email-schwarz@corscience.de> References: <1309270480-31918-1-git-send-email-schwarz@corscience.de> <1309270480-31918-3-git-send-email-schwarz@corscience.de> Message-ID: <4E0C5218.2060209@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tuesday 28 June 2011 07:44 PM, simonschwarzcor at googlemail.com wrote: > Deactivates caching in SPL. Add call to preloader_console_init for early console output. > > Signed-off-by: Simon Schwarz > -- > > diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c > index 6c2a132..bb38289 100644 > --- a/arch/arm/cpu/armv7/omap3/board.c > +++ b/arch/arm/cpu/armv7/omap3/board.c > @@ -37,6 +37,7 @@ > #include > #include > #include > +#include > > extern omap3_sysinfo sysinfo; > > @@ -166,10 +167,15 @@ void s_init(void) > > try_unlock_memory(); > > +#ifdef CONFIG_PRELOADER > + v7_flush_cache_all(); > +#endif > + Flush is not needed for initialization. Invalidation is enough. Indeed flush could be dangerous. > /* > * Right now flushing at low MPU speed. > * Need to move after clock init > */ > +#ifndef CONFIG_PRELOADER > invalidate_dcache(get_device_type()); > #ifndef CONFIG_ICACHE_OFF Unless you are enabling d-cache invalidate is also not needed. Please note that enabling d-cache in SPL has some complexities. Please see this thread for details: http://lists.denx.de/pipermail/u-boot/2011-May/092865.html > icache_enable(); With my armv7 cache maintenance series that is now available at u-boot- arm/master, I-cache will be invalidated and enabled in start.S itself unless CONFIG_SYS_I_CACHE_OFF is set. best regards, Aneesh