[U-Boot] [PATCH 2/4 v3] musb: Add Phy programming for using external Vbus

Ajay Kumar Gupta
2010-06-10T05:50:48Z

MUSB PHY on OMAP3EVM Rev >= E uses external Vbus supply to support
500mA of power.We need to program MUSB PHY to use external Vbus
for this purpose.

Adding 'extvbus' member in musb_config structure which should be set
by all the boards where MUSB interface is using external Vbus supply.

Also added ULPI bus control register read/write abstraction for
Blackfin processor as it doesn't have ULPI registers.

CC: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
---
Changes from v2:
Added 'return 0' in Blackfin version if ulpi read function.

drivers/usb/musb/musb_core.c | 7 +++++++
drivers/usb/musb/musb_core.h | 30 +++++++++++++++++++++++++++++-
2 files changed, 36 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 7766069..dc740cf 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -34,6 +34,7 @@ void musb_start(void)
{
#if defined(CONFIG_MUSB_HCD)
u8 devctl;
+ u8 busctl;
#endif

/* disable all interrupts */
@@ -45,6 +46,12 @@ void musb_start(void)
/* put into basic highspeed mode and start session */
writeb(MUSB_POWER_HSENAB, &musbr->power);
#if defined(CONFIG_MUSB_HCD)
+ /* Program PHY to use EXT VBUS if required */
+ if (musb_cfg.extvbus == 1) {
+ busctl = musb_read_ulpi_buscontrol(musbr);
+ musb_write_ulpi_buscontrol(musbr, busctl | ULPI_USE_EXTVBUS);
+ }
+
devctl = readb(&musbr->devctl);
writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl);
#endif
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 9a1fb4f..4771876 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -112,7 +112,10 @@ struct musb_regs {
u16 rxfifoadd;
u32 vcontrol;
u16 hwvers;
- u16 reserved2[5];
+ u16 reserved2a[1];
+ u8 ulpi_busctl;
+ u8 reserved2b[1];
+ u16 reserved2[3];
u8 epinfo;
u8 raminfo;
u8 linkinfo;
@@ -181,6 +184,10 @@ struct musb_regs {
#define MUSB_DEVCTL_HR 0x02
#define MUSB_DEVCTL_SESSION 0x01

+/* ULPI VBUSCONTROL */
+#define ULPI_USE_EXTVBUS 0x01
+#define ULPI_USE_EXTVBUSIND 0x02
+
/* TESTMODE */
#define MUSB_TEST_FORCE_HOST 0x80
#define MUSB_TEST_FIFO_ACCESS 0x40
@@ -341,6 +348,7 @@ struct musb_config {
struct musb_regs *regs;
u32 timeout;
u8 musb_speed;
+ u8 extvbus;
};

/* externally defined data */
@@ -361,6 +369,26 @@ extern void read_fifo(u8 ep, u32 length, void *fifo_data);
# define readb(addr) (u8)bfin_read16(addr)
# undef writeb
# define writeb(b, addr) bfin_write16(addr, b)
+/*
+ * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
+ * However, it has no ULPI support - so there are no registers at all.
+ * That means accesses to ULPI_BUSCONTROL have to be abstracted away.
+ */
+static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
+{
+ return 0;
+}
+static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
+{}
+#else
+static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
+{
+ return readb(&musbr->ulpi_busctl);
+}
+static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
+{
+ writeb(val, &musbr->ulpi_busctl);
+}
#endif

#endif /* __MUSB_HDRC_DEFS_H__ */
--
1.6.2.4