[U-Boot] i.MX51: FEC: Cache coherency problem?

[Aneesh V <aneesh@ti.com>]

Hi Anton,

On Tuesday 19 July 2011 11:44 PM, Anton Staaf wrote:
[snip ..]

>      There are a number of possible solutions:
>
>      1) Modify the invalidate code to first read the partial cache line
>      and then invalidate and then write back just the valid part of the
>      line.  This suffers from a race condition with concurrent code in
>      interrupt handlers or other CPUs.

How do you propose to implement this?

Are you suggesting something like momentarily turning off D-cache, read
the memory content into registers, enable cache again, mix the memory
content in registers with the cache content and then flush, or
something like that? I am afraid this will be way too complex if at all
viable.

I don't see any other easy option. Am I missing something?

best regards,
Aneesh