From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aneesh V Date: Wed, 20 Jul 2011 14:07:10 +0530 Subject: [U-Boot] i.MX51: FEC: Cache coherency problem? In-Reply-To: References: <20110718171836.67bfe605@archvile> <4E246569.9020404@denx.de> <20110719094406.686e2a45@archvile> <4E253E78.4050801@aribaud.net> <20110719103702.087d4254@archvile> <4E2543B6.1060505@ti.com> <4E2548DE.6060705@aribaud.net> <4E259670.8030706@comcast.net> Message-ID: <4E2693B6.1050809@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Anton, On Tuesday 19 July 2011 11:44 PM, Anton Staaf wrote: [snip ..] > There are a number of possible solutions: > > 1) Modify the invalidate code to first read the partial cache line > and then invalidate and then write back just the valid part of the > line. This suffers from a race condition with concurrent code in > interrupt handlers or other CPUs. How do you propose to implement this? Are you suggesting something like momentarily turning off D-cache, read the memory content into registers, enable cache again, mix the memory content in registers with the cache content and then flush, or something like that? I am afraid this will be way too complex if at all viable. I don't see any other easy option. Am I missing something? best regards, Aneesh