From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Wed, 20 Jul 2011 15:02:01 +0200 Subject: [U-Boot] i.MX51: FEC: Cache coherency problem? In-Reply-To: <4E25E4EC.70904@comcast.net> References: <20110718171836.67bfe605@archvile> <4E246569.9020404@denx.de> <20110719094406.686e2a45@archvile> <4E253E78.4050801@aribaud.net> <20110719103702.087d4254@archvile> <4E2543B6.1060505@ti.com> <4E2548DE.6060705@aribaud.net> <4E259670.8030706@comcast.net> <4E25E4EC.70904@comcast.net> Message-ID: <4E26D1C9.50200@aribaud.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Le 19/07/2011 22:11, J. William Campbell a ?crit : > If this is true, then it means that the cache is of type write-back (as > opposed to write-thru). From a (very brief) look at the arm7 manuals, it > appears that both types of cache may be present in the cpu. Do you know > how this operates? Usually, copyback (rather than writeback) and writethough are modes of operation, not cache types. Amicalement, -- Albert.