From: Albert ARIBAUD <albert.u.boot@aribaud.net>
To: u-boot@lists.denx.de
Subject: [U-Boot] i.MX51: FEC: Cache coherency problem?
Date: Sat, 23 Jul 2011 15:04:21 +0200 [thread overview]
Message-ID: <4E2AC6D5.1010709@aribaud.net> (raw)
In-Reply-To: <20110721084803.6d7b1278@archvile>
Le 21/07/2011 08:48, David Jander a ?crit :
>> However, it is still correct that copying from an non-cached area is
>> slower than from cached areas, because of burst reads vs. individual
>> reads. However, I doubt that the u-boot user can tell the difference, as
>> the network latency will far exceed the difference in copy time.
That's assuming cache is only for networking. There can be DMA engines
in a lot of other peripherals which do not have the same latency as
network (and then, even for networking, TFTP can be done from a very
nearby server, possibly even on the same Ethernet segment).
>> The
>> question is, which is easier to do, and that is probably a matter of
>> opinion. However, it is safe to say that so far a cached solution has
>> eluded us. That may be changing, but it would still be nice to know how
>> to allocate a section of un-cached RAM in the ARM processor, in so far
>> as the question has a single answer! That would allow easy portability
>> of drivers that do not know about caches, of which there seems to be many.
That is one approach, which I think prevents cache from being used
beyond caching pure CPU-used DRAM.
> I agree. Unfortunately, my time is up for now, and I can't go on with trying
> to fix this driver. Maybe I'll pick up after my vacation.
> As for now I settled for the ugly solution of keeping dcache disabled while
> ethernet is being used :-(
Make sure you flush before disabling. :)
> IMHO, doing cache maintenance all over the driver is not an easy or nice
> solution. Implementing a non-cached memory pool in the MMU and a corresponding
> dma_malloc() sounds like much more universally applicable to any driver.
I think cache maintenance is feasible if one makes sure the cached areas
used by the driver are properly aligned, which simplifies things a lot:
you don't have to care for flush-invalidate or just-in-time invalidate,
you just have to flush before sending and invalidate before reading.
> Best regards,
Amicalement,
--
Albert.
next prev parent reply other threads:[~2011-07-23 13:04 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-18 15:18 [U-Boot] i.MX51: FEC: Cache coherency problem? David Jander
2011-07-18 16:16 ` Aneesh V
2011-07-19 7:26 ` David Jander
2011-07-19 11:07 ` Matthias Weißer
2011-07-19 11:17 ` David Jander
2011-07-19 11:20 ` Wolfgang Denk
2011-07-19 12:10 ` David Jander
2011-07-20 6:29 ` David Jander
2011-07-20 8:56 ` Albert ARIBAUD
2011-07-20 9:21 ` David Jander
2011-07-20 10:29 ` Aneesh V
2011-07-20 11:31 ` David Jander
2011-07-20 12:05 ` Aneesh V
2011-07-19 11:19 ` Wolfgang Denk
2011-07-19 14:31 ` Matthias Weißer
2011-07-19 11:51 ` Aneesh V
2011-07-18 16:55 ` Stefano Babic
2011-07-19 7:44 ` David Jander
2011-07-19 8:21 ` Albert ARIBAUD
2011-07-19 8:37 ` David Jander
2011-07-19 8:43 ` Aneesh V
2011-07-19 8:58 ` David Jander
2011-07-19 9:11 ` Albert ARIBAUD
2011-07-19 11:50 ` Aneesh V
2011-07-19 11:42 ` Aneesh V
2011-07-19 9:05 ` Albert ARIBAUD
2011-07-19 14:36 ` J. William Campbell
2011-07-19 15:17 ` David Jander
2011-07-19 18:14 ` Anton Staaf
2011-07-19 20:11 ` J. William Campbell
2011-07-20 13:02 ` Albert ARIBAUD
[not found] ` <4E26DF9D.5070709@comcast.net>
[not found] ` <4E26E7AA.9070001@aribaud.net>
2011-07-20 15:36 ` J. William Campbell
2011-07-21 6:48 ` David Jander
2011-07-23 13:04 ` Albert ARIBAUD [this message]
2011-07-23 15:35 ` J. William Campbell
2011-07-20 8:37 ` Aneesh V
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