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From: Aneesh V <aneesh@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH RESEND v2] armv7: Disable D cache for goni target (s5p)
Date: Fri, 29 Jul 2011 15:43:53 +0530	[thread overview]
Message-ID: <4E3287E1.7020804@ti.com> (raw)
In-Reply-To: <CACRpkdZRvqRH5z9RjewvdLEC4-oF7VYL01wwX4bUHyQ5Q9r=7A@mail.gmail.com>

Hi Linus,

On Friday 29 July 2011 04:04 AM, Linus Walleij wrote:
> On Thu, Jul 28, 2011 at 7:04 AM, Minkyu Kang<promsoft@gmail.com>  wrote:
>> Dear Linus Walleij,
>>
>> On 18 July 2011 19:35, Linus Walleij<linus.walleij@linaro.org>  wrote:
>>> On Mon, Jul 18, 2011 at 9:23 AM, Lukasz Majewski<l.majewski@samsung.com>  wrote:
>>>
>>>> Disable D cache for goni target (s5p) - rationale:
>>>>
>>>> 1. Before change introduced in commit
>>>> SHA1:c2dd0d45540397704de9b13287417d21049d34c6 the D-cache for
>>>> GONI target was disabled. This change was supposed to
>>>> preserve this state.
>>>
>>> I had exactly the same rationale for disabling cache on the Integrator - it
>>> used to be off now it's default on and doesn't work - but that patch was
>>> NAK:ed by Wolfgang.
>>>
>>
>> Could you please give me the link of that thread?
>
> Me:
> http://marc.info/?l=u-boot&m=131066804010454&w=2

I hadn't noticed this thread before. Here are my thoughts on your
problem:

I think the fundamental problem is that caching was enabled for ARM
without putting the cache maintenance functions in place. At a minimum,
we need a few flush and invalidate functions. I worked on this for
armv7, but similar things need to be done for earlier architectures if
you have to enable caching. Once we have these cache maintenance
functions, they need to be used in the following scenarios to avoid
coherency issues.

1. Drivers using DMA:
i. Flush the buffer before initiating a memory to peripheral DMA.
ii. Invalidate the buffer after a peripheral to memory DMA (before
MPU reads it)

2. Cleanup before Linux:
Flush the entire SDRAM and disable the cache.

I think you are hit by not doing 2 properly. If you have dirty entries
in the cache when Linux boots you will have coherency issues. I had
faced similar issues when I had some issues in armv7
cleanup_before_linux(). I had to do an extra invalidate to solve it.
Please see how this has been done for armv7 in arch/arm/cpu/armv7/cpu.c
in function cleanup_before_linux().

In some other cases there are problems due to (1) above. In any case,
the starting point really is to make sure that you have the required
set of maintenance functions for your architecture revision. We may not
need maintenance functions for each architecture revision depending on
the backward compatibility of the successive revisions. I have not
looked into those details though.

best regards,
Aneesh

  reply	other threads:[~2011-07-29 10:13 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-07-18  7:23 [U-Boot] [PATCH RESEND v2] armv7: Disable D cache for goni target (s5p) Lukasz Majewski
2011-07-18 10:35 ` Linus Walleij
2011-07-28  5:04   ` Minkyu Kang
2011-07-28 22:34     ` Linus Walleij
2011-07-29 10:13       ` Aneesh V [this message]
2011-07-29 10:31         ` Chander Kashyap
2011-07-29 10:53           ` Aneesh V
2011-07-31  8:18         ` Linus Walleij
2011-08-01  6:20           ` Aneesh V
2011-07-29  2:56     ` Chander Kashyap

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