[U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache

Albert ARIBAUD
2011-08-07T07:07:42Z

Hi Bill,

Le 06/08/2011 01:04, J. William Campbell a ?crit :

> Hi All,
> I am interested in this last statement in particular, that
> Linux allows non-cache aligned buffers for DMA. In a previous discussion
> series, we demonstrated why it was IMPOSSIBLE for a non-cache aligned
> DMA buffer to work in conjunction with a "write back" type cache. To be
> clear, by write-back, we mean a cache system that has a single dirty bit
> per cache line, and that if there are stores to any addresses in that
> line, the ENTIRE LINE will be written back into memory, not just the
> changed data. I also seem to recall that the ARM V7 caches were defined
> as write back, but I am not an ARM person so I don't know for sure what
> kind of cache we are talking about here. If it is write-back, there is
> only one possible solution that always works. Write-through will work
> with un-aligned buffers if the correct flushes and invalidates are
> present. In that case, buffer alignment is not so important. However, if
> the same driver is to be used in both cases, it must use cache-aligned
> buffers only.

The type of caches in ARM vary greatly, can be configurable at runtime,
with the ability to have settings per regions for some implementations,
so we could use either write-through or write-back, even in a single run.

I don't like however the idea of solving the issue discussed here by
adding constraints on the type of caching, because it has other effects
than helping work in an out-of-spec case: it lowers DMA buffer write
throughput, it adds complexity in cache configuration on architectures
which can handle cache regions, and on those which cannot, it causes a
general RAM write performance hit -- all this for an out-of-spec case
which is not really complicated to turn into an in-spec case.

> Best Regards,
> Bill Campbell

Amicalement,
--
Albert.