From mboxrd@z Thu Jan  1 00:00:00 1970
From: Aneesh V <aneesh@ti.com>
Date: Mon, 08 Aug 2011 13:54:10 +0530
Subject: [U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate
	D-Cache
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Hi Albert,

On Sunday 07 August 2011 12:25 PM, Albert ARIBAUD wrote:
> Hi Aneesh,
>
> (cutting quotation for readability)
>
> Le 05/08/2011 16:59, Aneesh V a ?crit :
>> Hi Albert,
>
>> I don't dispute that having buffers aligned is the ideal scenario. The
>> question is about error-handling the situation when this requirement is
>> not met.
>
> I understand what you're trying to achieve in this respect, that is,
> make the code as correct as it can be under unspecified conditions. I
> believe we are differing in how we construe 'as correct as it can be':
> you want to make the implementation of the called function as correct as
> it can be' at the expense of introducing a non-intuitive behavior (flush
> while invalidating), while I prefer the overall system to be as correct
> as it can be by 'doing exactly what it says on the tin', i.e.
> invalidating only.

I understand your point of view now. I shall update my cache fix series
to invalidate only the aligned part of the buffer and to print a big
warning when the buffer is not aligned.

best regards,
Aneesh