From: Aneesh V <aneesh@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] armv7:cache: D cache line size read method
Date: Fri, 12 Aug 2011 14:32:52 +0530 [thread overview]
Message-ID: <4E44EC3C.5010808@ti.com> (raw)
In-Reply-To: <1313137442-8378-1-git-send-email-l.majewski@samsung.com>
On Friday 12 August 2011 01:54 PM, Lukasz Majewski wrote:
> This commit adds support for reading the D cache line size for armv7
> architecture.
>
> The get_dcache_line_size() function is supposed to work in conjunction
> with memalign call to provide D cache aligned DMA buffers.
>
> Signed-off-by: Lukasz Majewski<l.majewski@samsung.com>
> Signed-off-by: Kyungmin Park<kyungmin.park@samsung.com>
> CC: Aneesh V<aneesh@ti.com>
> CC: Albert ARIBAUD<albert.u.boot@aribaud.net>
> ---
> arch/arm/cpu/armv7/cache_v7.c | 25 +++++++++++++++++++++++++
> include/common.h | 1 +
> 2 files changed, 26 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index 3e1e1bf..bd0b1a8 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -246,6 +246,21 @@ static void v7_inval_tlb(void)
> CP15ISB;
> }
>
> +/* Read the cache line size (bytes) */
> +static int v7_dcache_line_size(void)
> +{
> + u32 ccsidr, log2_line_len;
> +
> + ccsidr = get_ccsidr();
> +
> + log2_line_len = ((ccsidr& CCSIDR_LINE_SIZE_MASK)>>
> + CCSIDR_LINE_SIZE_OFFSET) + 2;
> + /* Converting from words to bytes */
> + log2_line_len += 2;
> +
> + return 1<< log2_line_len;
> +}
> +
> void invalidate_dcache_all(void)
> {
> v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
> @@ -303,6 +318,11 @@ void flush_cache(unsigned long start, unsigned long size)
> {
> flush_dcache_range(start, start + size);
> }
> +
> +int get_dcache_line_size(void)
> +{
> + return v7_dcache_line_size();
> +}
> #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
> void invalidate_dcache_all(void)
> {
> @@ -327,6 +347,11 @@ void arm_init_before_mmu(void)
> void flush_cache(unsigned long start, unsigned long size)
> {
> }
> +
> +int get_dcache_line_size(void)
> +{
> + return 0;
> +}
Does memalign() take 0 as input and if so what is the output. The GNU C
library seems to mandate only that it's a power of 2. But the following
man page seems to says that "The value of alignment must be a power of
two and must be greater than or equal to the size of a word."
http://www.s-gms.ms.edus.si/cgi-bin/man-cgi?memalign+3C
Also, you seem to be using get_dcache_line_size() in MMC driver. Is
this function defined for all platforms. Maybe, you must implement a
weakly linked default function for all platforms?
best regards,
Aneesh
next prev parent reply other threads:[~2011-08-12 9:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-12 8:24 [U-Boot] [PATCH] armv7:cache: D cache line size read method Lukasz Majewski
2011-08-12 8:58 ` Albert ARIBAUD
2011-08-12 9:16 ` Aneesh V
2011-08-12 9:48 ` Albert ARIBAUD
2011-08-16 18:32 ` Anton Staaf
2011-08-12 9:02 ` Aneesh V [this message]
2011-08-12 9:46 ` Lukasz Majewski
2011-08-16 10:31 ` [U-Boot] [PATCH v2] " Lukasz Majewski
2011-08-16 11:24 ` Sergei Shtylyov
2011-08-16 12:01 ` [U-Boot] [RESEND PATCH " Lukasz Majewski
2011-08-17 8:51 ` [U-Boot] [PATCH v3] " Lukasz Majewski
2011-08-17 16:28 ` Albert ARIBAUD
2011-08-18 6:46 ` [U-Boot] [RESEND PATCH " Lukasz Majewski
2011-08-23 6:13 ` [U-Boot] [PATCH v4] dcache: " Lukasz Majewski
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