From: Aneesh V <aneesh@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] d-cache enable
Date: Fri, 12 Aug 2011 17:46:41 +0530 [thread overview]
Message-ID: <4E4519A9.3080804@ti.com> (raw)
In-Reply-To: <20110812134151.46d0e47c@lmajewski.digital.local>
Hi Lukasz,
On Friday 12 August 2011 05:11 PM, Lukasz Majewski wrote:
> Hi Aneesh,
>
> On Fri, 12 Aug 2011 16:29:25 +0530
> Aneesh V <aneesh@ti.com> wrote:
>
>> Hi Lukasz,
>>
>> On Tuesday 09 August 2011 08:11 PM, Lukasz Majewski wrote:
>>> Dear all,
>>>
>>> As we know dcache is now enabled in u-boot.
>>>
>>> I'm trying to make the S5P Goni target working with d-cache enabled.
>>> There are some patches and ideas appearing on the list (e.g.
>>> http://patchwork.ozlabs.org/patch/109199/ made by Aneesh V)
>>>
>>>
>>> I'm currently using the u-boot/master branch,
>>> SHA1: d26a82023af5771462f7223241ed18cfb7965f71
>>>
>>> After some research I can say that flush_dcache_all() and
>>> invalidate_dcache_all() are working(at least on my target).
>>>
>>> However I'm planning to use the "range" versions:
>>> flush_dcache_range((unsigned long) (buf), sizeof(buf));
>>> invalidate_dcache_range((unsigned long) (buf), sizeof(buf));
>>>
>>> Those versions are not working on the Cortex-A8 (armv7) GONI target.
>>> I'd like to ask if anybody was trying to use those functions
>>> (defined at cache_v7.c) on other armv7 targets?
>>
>> I have tested cache on OMAP3(Cortex-A8) and OMAP4(Cortex-A9). Why do
>> you think it's not working for you. Did you run some tests? If so,
>> what was the result? Are you enabling only L1 or both L1 & L2? Can
>> you try the attached crude patch for testing caches. You might have
>> to change the addresses according to your platform. If you could run
>> it, let me know the results.
>>
>> best regards,
>> Aneesh
>
> It is embarrassing to admit, but I've __wrongly__ assumed that *_range()
> functions are accepting the start address and range for
> invalidation/flushing.
>
There is already some confusion around that. As pointed out by Reinhard
some MIPS implementations actually interpret the parameters that way.
But at least for arm, it's [strat, stop).
> Yes, they are working when I've realized how to use them :-).
Good to know that.
best regards,
Aneesh
next prev parent reply other threads:[~2011-08-12 12:16 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-01 11:18 [U-Boot] [PATCH v 0/3] arm: changes in cache handling Aneesh V
2011-08-01 11:18 ` [U-Boot] [PATCH v 1/3] arm: do not force d-cache enable on all boards Aneesh V
2011-08-01 16:33 ` Jason Liu
2011-08-01 16:46 ` Jason Liu
2011-08-01 19:45 ` Wolfgang Denk
2011-08-01 19:53 ` Albert ARIBAUD
2011-08-02 14:35 ` Jason Liu
2011-08-02 15:58 ` Albert ARIBAUD
2011-08-05 15:07 ` Aneesh V
2011-08-07 6:20 ` Albert ARIBAUD
2011-08-09 11:10 ` [U-Boot] [PATCH 0/4] arm: changes in cache handling Aneesh V
2011-08-09 11:25 ` Aneesh V
2011-08-09 11:10 ` [U-Boot] [PATCH 1/4] arm: do not force d-cache enable on all boards Aneesh V
2011-08-09 11:10 ` [U-Boot] [PATCH 2/4] omap: enable caches at system start-up Aneesh V
2011-08-09 11:10 ` [U-Boot] [PATCH 3/4] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-09 11:10 ` [U-Boot] [PATCH 4/4] armv7: cache: remove flush on un-aligned invalidate Aneesh V
2011-08-09 16:39 ` Anton Staaf
2011-08-10 6:29 ` Albert ARIBAUD
2011-08-10 6:48 ` Aneesh V
2011-08-10 18:11 ` Anton Staaf
2011-08-11 6:29 ` Aneesh V
2011-08-09 11:34 ` [U-Boot] [PATCH v2 0/4] arm: changes in cache handling Aneesh V
2011-08-09 11:34 ` [U-Boot] [PATCH v2 1/4] arm: do not force d-cache enable on all boards Aneesh V
2011-08-09 14:41 ` [U-Boot] d-cache enable Lukasz Majewski
2011-08-12 10:59 ` Aneesh V
2011-08-12 11:41 ` Lukasz Majewski
2011-08-12 12:16 ` Aneesh V [this message]
2011-08-12 12:21 ` Albert ARIBAUD
2011-08-12 12:32 ` Reinhard Meyer
2011-08-12 12:36 ` Albert ARIBAUD
2011-08-12 13:08 ` Lukasz Majewski
2011-08-12 13:19 ` Albert ARIBAUD
2011-08-09 11:34 ` [U-Boot] [PATCH v2 2/4] omap: enable caches at system start-up Aneesh V
2011-08-09 11:34 ` [U-Boot] [PATCH v2 3/4] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-09 11:34 ` [U-Boot] [PATCH v2 4/4] armv7: cache: remove flush on un-aligned invalidate Aneesh V
2011-08-11 14:35 ` [U-Boot] [PATCH v3 0/4] arm: changes in cache handling Aneesh V
2011-08-13 10:09 ` Albert ARIBAUD
2011-08-15 7:40 ` V, Aneesh
2011-08-11 14:35 ` [U-Boot] [PATCH v3 1/4] arm: do not force d-cache enable on all boards Aneesh V
2011-08-14 11:09 ` Simon Guinot
2011-08-15 7:34 ` V, Aneesh
2011-08-16 14:33 ` [U-Boot] [PATCH v4 " Aneesh V
2011-08-11 14:35 ` [U-Boot] [PATCH v3 2/4] omap: enable caches at system start-up Aneesh V
2011-08-11 14:35 ` [U-Boot] [PATCH v3 3/4] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-11 14:35 ` [U-Boot] [PATCH v3 4/4] armv7: cache: remove flush on un-aligned invalidate Aneesh V
2011-08-01 11:18 ` [U-Boot] [PATCH v 2/3] omap: enable caches at system start-up Aneesh V
2011-08-01 11:18 ` [U-Boot] [PATCH v 3/3] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-05 10:29 ` [U-Boot] [PATCH v 0/3] arm: changes in cache handling Aneesh V
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4E4519A9.3080804@ti.com \
--to=aneesh@ti.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox