[U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations

Lei Wen
2011-08-19T10:17:31Z

Hi Hong,

On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu <hong.xu@atmel.com> wrote:
> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
> into this file.
>
> Signed-off-by: Hong Xu <hong.xu@atmel.com>
> Tested-by: Elen Song <elen.song@atmel.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> ---
> Since V1
> ? ?Modified copyright line
> ? ?Fix for compiling warnings
> ? ?Changed the way to use CONFIG_SYS_CACHELINE_SIZE
> ? ?When unaligned buffer detected, emit ERROR instead of WARNING
>
> ? ?Do not make a common v5,v6 cache file. It seems arm946 is lack of
> ? ?Test-and-Clean DCache operation. And maybe more differents...
>
> ?arch/arm/cpu/arm926ejs/Makefile | ? ?2 +-
> ?arch/arm/cpu/arm926ejs/cache.c ?| ?135 +++++++++++++++++++++++++++++++++++++++
> ?2 files changed, 136 insertions(+), 1 deletions(-)
> ?create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>

This patch series don't works for me. My board is also arm926ejs
based, and its configure as dkb_config;
The error message as below:
ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - start address 0x1fe7be30 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - stop address 0x1fe7c030 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - start address 0x1fe7be28 not aligned to
cache line size(32 bytes)
ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to
cache line size(32 bytes)

Do you have any hint for this?

Best regards,
Lei