[U-Boot] [PATCH v3] net: ll_temac: Add LL TEMAC driver to u-boot

[Michal Simek <monstr@monstr.eu>]

Dear Wolfgang Denk,

Wolfgang Denk wrote:
> Dear Michal Simek,
> 
> In message <4E5F85DA.4080403@monstr.eu> you wrote:
>>>> +static void sdma_out_be32(struct ll_priv *priv, u32 offset, u32 val)
>>>> +{
>>>> +	if (priv->mode & DCR_BIT)
>>>> +		mtdcr_local(priv->ctrl + offset, val);
>>>> +	else
>>>> +		out_be32((u32 *)(priv->ctrl + offset * 4), val);
>>>> +}
>>>> +
>>>> +static u32 sdma_in_be32(struct ll_priv *priv, u32 offset)
>>>> +{
>>>> +	if (priv->mode & DCR_BIT)
>>>> +		return mfdcr_local(priv->ctrl + offset);
>>>> +
>>>> +	return in_be32((u32 *)(priv->ctrl + offset * 4));
>>>> +}
>>> Can we please get rid of these functions?  As mentioned many, many
>>> times before, we discourage all use of "base address plus offset" to
>>> access any device registers etc.
>>>
>>> These functions here re-introduce such accesses, and this is something
>>> I will not accept.
>> Ok. How to do it?
>>
>> For bus access it is necessary to use 4B offsets for DCR just 1B
>> and one system can contains two MACs where the first use 4B offset and the second
>> 1B.
> 
> I don't think your description here matches the code above.  With "1
> byte offsets" you would be doing all unaligned bus accesses.


Let me show it on example.
on MB or PPC system with bus:
DMA is in memory controller on 32bit address + sdma DMA port offset.

DMA : Sdma offset(www.xilinx.com/support/documentation/ip_documentation/mpmc.pdf page 54 and 55)
0   : 0x0
1   : 0x80
2   : 0x100
3   : 0x180
...
7   : 0x380

Let me assume that MPMC is at 0x12340000
The first reg for DMA2 accessed through bus is at 0x12340100 offset the second at 0x12340104, the third 0x12340108 etc.

On PPC system with DCR is special connection between memory controller through DCR bus. Handling is done
with mfdcr_local and mtdcr_local functions.

DMA : Sdma address ranges (www.xilinx.com/support/documentation/user_guides/ug200.pdf page 261 and 299)
0   : 0x80-0x90
1   : 0x98-0xA8
2   : 0xB0-0xC0
3   : 0xC8-0xD8

The first reg for DMA2 accessed trough DCR is at 0xB0, the second at 0xB1, etc..

Regards,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian