[U-Boot] [PATCH 08/31] M28EVK: Enable FEC0 and FEC1

Marek Vasut
2011-09-08T20:42:36Z

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
---
board/denx/m28evk/m28evk.c | 109 ++++++++++++++++++++++++++++++++++++++++++++
include/configs/m28evk.h | 22 +++++++--
2 files changed, 127 insertions(+), 4 deletions(-)

diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
index d3e6173..fea0227 100644
--- a/board/denx/m28evk/m28evk.c
+++ b/board/denx/m28evk/m28evk.c
@@ -28,10 +28,15 @@
#include <asm/arch/regs-common.h>
#include <asm/arch/regs-base.h>
#include <asm/arch/regs-clkctrl.h>
+#include <asm/arch/regs-ocotp.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/mx28.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -89,3 +94,107 @@ int board_mmc_init(bd_t *bis)
return mxsmmc_initialize(bis, 0, m28_mmc_wp);
}
#endif
+
+#ifdef CONFIG_CMD_NET
+
+#define MII_OPMODE_STRAP_OVERRIDE 0x16
+#define MII_PHY_CTRL1 0x1e
+#define MII_PHY_CTRL2 0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+ miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+ miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+ if (phy == 3)
+ miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+ CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC0");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC0 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC0 mii postcall\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC1");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC1 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC1 mii postcall\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
+
+#define MXS_OCOTP_MAX_TIMEOUT 1000000
+void imx_get_mac_from_fuse(char *mac)
+{
+ struct mx28_ocotp_regs *ocotp_regs =
+ (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+ uint32_t data;
+
+ memset(mac, 0, 6);
+
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+ if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+ MXS_OCOTP_MAX_TIMEOUT)) {
+ printf("MXS FEC: Can't get MAC from OCOTP\n");
+ return;
+ }
+
+ data = readl(&ocotp_regs->hw_ocotp_cust0);
+
+ mac[0] = 0x00;
+ mac[1] = 0x04;
+ mac[2] = (data >> 24) & 0xff;
+ mac[3] = (data >> 16) & 0xff;
+ mac[4] = (data >> 8) & 0xff;
+ mac[5] = data & 0xff;
+}
+#else
+void imx_get_mac_from_fuse(char *mac)
+{
+ memset(mac, 0, 6);
+}
+#endif
+
+#endif
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 1b4db7b..9e0d705 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -44,13 +44,14 @@
#define CONFIG_DOS_PARTITION

#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR

/*
@@ -106,6 +107,19 @@
#endif

/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE RMII
+#endif
+
+/*
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG
--
1.7.5.4