[U-Boot] [PATCH 21/31] iMX28: Add BCH and GPMI register definitions

Marek Vasut
2011-09-08T20:42:49Z

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
---
arch/arm/include/asm/arch-mx28/regs-bch.h | 226 ++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mx28/regs-gpmi.h | 218 +++++++++++++++++++++++++++
2 files changed, 444 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx28/regs-bch.h
create mode 100644 arch/arm/include/asm/arch-mx28/regs-gpmi.h

diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h
new file mode 100644
index 0000000..b788895
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-bch.h
@@ -0,0 +1,226 @@
+/*
+ * Freescale i.MX28 BCH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_BCH_H__
+#define __REGS_BCH_H__
+
+struct mx28_bch_regs {
+ mx28_reg(hw_bch_ctrl)
+ mx28_reg(hw_bch_status0)
+ mx28_reg(hw_bch_mode)
+ mx28_reg(hw_bch_encodeptr)
+ mx28_reg(hw_bch_dataptr)
+ mx28_reg(hw_bch_metaptr)
+
+ uint32_t reserved[4];
+
+ mx28_reg(hw_bch_layoutselect)
+ mx28_reg(hw_bch_flash0layout0)
+ mx28_reg(hw_bch_flash0layout1)
+ mx28_reg(hw_bch_flash1layout0)
+ mx28_reg(hw_bch_flash1layout1)
+ mx28_reg(hw_bch_flash2layout0)
+ mx28_reg(hw_bch_flash2layout1)
+ mx28_reg(hw_bch_flash3layout0)
+ mx28_reg(hw_bch_flash3layout1)
+ mx28_reg(hw_bch_dbgkesread)
+ mx28_reg(hw_bch_dbgcsferead)
+ mx28_reg(hw_bch_dbgsyndegread)
+ mx28_reg(hw_bch_dbgahbmread)
+ mx28_reg(hw_bch_blockname)
+ mx28_reg(hw_bch_version)
+};
+
+#define BCH_CTRL_SFTRST (1 << 31)
+#define BCH_CTRL_CLKGATE (1 << 30)
+#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
+#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
+#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
+#define BCH_CTRL_M2M_ENCODE (1 << 17)
+#define BCH_CTRL_M2M_ENABLE (1 << 16)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
+#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
+#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
+#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
+#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
+
+#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
+#define BCH_STATUS0_HANDLE_OFFSET 20
+#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
+#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
+#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
+#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
+#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
+#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
+#define BCH_STATUS0_ALLONES (1 << 4)
+#define BCH_STATUS0_CORRECTED (1 << 3)
+#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
+
+#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
+#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
+
+#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
+#define BCH_ENCODEPTR_ADDR_OFFSET 0
+
+#define BCH_DATAPTR_ADDR_MASK 0xffffffff
+#define BCH_DATAPTR_ADDR_OFFSET 0
+
+#define BCH_METAPTR_ADDR_MASK 0xffffffff
+#define BCH_METAPTR_ADDR_OFFSET 0
+
+#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30)
+#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
+#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28)
+#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
+#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26)
+#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
+#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24)
+#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
+#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22)
+#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
+#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20)
+#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
+#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18)
+#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
+#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16)
+#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
+#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14)
+#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
+#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12)
+#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
+#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10)
+#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
+#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8)
+#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
+#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6)
+#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
+#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4)
+#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
+#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2)
+#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
+#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0)
+#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
+
+#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
+#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
+#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
+#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
+#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
+#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
+#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
+#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
+
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
+#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
+#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
+#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
+#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
+
+#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
+#define BCH_DEBUG0_RSVD1_OFFSET 27
+#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
+#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
+#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
+#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
+#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
+#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
+#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
+#define BCH_DEBUG0_RSVD0_OFFSET 6
+#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
+#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
+
+#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGKESREAD_VALUES_OFFSET 0
+
+#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
+
+#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
+
+#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
+
+#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
+#define BCH_BLOCKNAME_NAME_OFFSET 0
+
+#define BCH_VERSION_MAJOR_MASK (0xff << 24)
+#define BCH_VERSION_MAJOR_OFFSET 24
+#define BCH_VERSION_MINOR_MASK (0xff << 16)
+#define BCH_VERSION_MINOR_OFFSET 16
+#define BCH_VERSION_STEP_MASK 0xffff
+#define BCH_VERSION_STEP_OFFSET 0
+
+#endif /* __REGS_BCH_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h
new file mode 100644
index 0000000..ae56cd6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-gpmi.h
@@ -0,0 +1,218 @@
+/*
+ * Freescale i.MX28 GPMI Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_GPMI_H__
+#define __REGS_GPMI_H__
+
+struct mx28_gpmi_regs {
+ mx28_reg(hw_gpmi_ctrl0)
+ mx28_reg(hw_gpmi_compare)
+ mx28_reg(hw_gpmi_eccctrl)
+ mx28_reg(hw_gpmi_ecccount)
+ mx28_reg(hw_gpmi_payload)
+ mx28_reg(hw_gpmi_auxiliary)
+ mx28_reg(hw_gpmi_ctrl1)
+ mx28_reg(hw_gpmi_timing0)
+ mx28_reg(hw_gpmi_timing1)
+
+ uint32_t reserved[4];
+
+ mx28_reg(hw_gpmi_data)
+ mx28_reg(hw_gpmi_stat)
+ mx28_reg(hw_gpmi_debug)
+ mx28_reg(hw_gpmi_version)
+};
+
+#define GPMI_CTRL0_SFTRST (1 << 31)
+#define GPMI_CTRL0_CLKGATE (1 << 30)
+#define GPMI_CTRL0_RUN (1 << 29)
+#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
+#define GPMI_CTRL0_LOCK_CS (1 << 27)
+#define GPMI_CTRL0_UDMA (1 << 26)
+#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
+#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
+#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
+#define GPMI_CTRL0_CS_MASK (0x7 << 20)
+#define GPMI_CTRL0_CS_OFFSET 20
+#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
+#define GPMI_CTRL0_ADDRESS_OFFSET 17
+#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
+#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
+#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
+#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
+
+#define GPMI_COMPARE_MASK_MASK (0xffff << 16)
+#define GPMI_COMPARE_MASK_OFFSET 16
+#define GPMI_COMPARE_REFERENCE_MASK 0xffff
+#define GPMI_COMPARE_REFERENCE_OFFSET 0
+
+#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
+#define GPMI_ECCCTRL_HANDLE_OFFSET 16
+#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
+#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
+#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
+#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
+#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
+
+#define GPMI_ECCCOUNT_COUNT_MASK 0xffff
+#define GPMI_ECCCOUNT_COUNT_OFFSET 0
+
+#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_PAYLOAD_ADDRESS_OFFSET 2
+
+#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_AUXILIARY_ADDRESS_OFFSET 2
+
+#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
+#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
+#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
+#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
+#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
+#define GPMI_CTRL1_BCH_MODE (1 << 18)
+#define GPMI_CTRL1_DLL_ENABLE (1 << 17)
+#define GPMI_CTRL1_HALF_PERIOD (1 << 16)
+#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
+#define GPMI_CTRL1_RDN_DELAY_OFFSET 12
+#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
+#define GPMI_CTRL1_DEV_IRQ (1 << 10)
+#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
+#define GPMI_CTRL1_BURST_EN (1 << 8)
+#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
+#define GPMI_CTRL1_DEV_RESET (1 << 3)
+#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
+#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
+#define GPMI_CTRL1_GPMI_MODE (1 << 0)
+
+#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
+#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
+#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
+#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
+#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
+
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
+
+#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
+#define GPMI_TIMING2_UDMA_TRP_OFFSET 24
+#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
+#define GPMI_TIMING2_UDMA_ENV_OFFSET 16
+#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
+#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
+#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
+
+#define GPMI_DATA_DATA_MASK 0xffffffff
+#define GPMI_DATA_DATA_OFFSET 0
+
+#define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
+#define GPMI_STAT_READY_BUSY_OFFSET 24
+#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
+#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
+#define GPMI_STAT_DEV7_ERROR (1 << 15)
+#define GPMI_STAT_DEV6_ERROR (1 << 14)
+#define GPMI_STAT_DEV5_ERROR (1 << 13)
+#define GPMI_STAT_DEV4_ERROR (1 << 12)
+#define GPMI_STAT_DEV3_ERROR (1 << 11)
+#define GPMI_STAT_DEV2_ERROR (1 << 10)
+#define GPMI_STAT_DEV1_ERROR (1 << 9)
+#define GPMI_STAT_DEV0_ERROR (1 << 8)
+#define GPMI_STAT_ATA_IRQ (1 << 4)
+#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
+#define GPMI_STAT_FIFO_EMPTY (1 << 2)
+#define GPMI_STAT_FIFO_FULL (1 << 1)
+#define GPMI_STAT_PRESENT (1 << 0)
+
+#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
+#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
+#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
+#define GPMI_DEBUG_DMA_SENSE_OFFSET 16
+#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
+#define GPMI_DEBUG_DMAREQ_OFFSET 8
+#define GPMI_DEBUG_CMD_END_MASK 0xff
+#define GPMI_DEBUG_CMD_END_OFFSET 0
+
+#define GPMI_VERSION_MAJOR_MASK (0xff << 24)
+#define GPMI_VERSION_MAJOR_OFFSET 24
+#define GPMI_VERSION_MINOR_MASK (0xff << 16)
+#define GPMI_VERSION_MINOR_OFFSET 16
+#define GPMI_VERSION_STEP_MASK 0xffff
+#define GPMI_VERSION_STEP_OFFSET 0
+
+#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
+#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
+#define GPMI_DEBUG2_BUSY (1 << 23)
+#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
+#define GPMI_DEBUG2_PIN_STATE_OFFSET 20
+#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
+#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
+#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
+#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
+#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
+#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
+#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
+#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
+#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
+#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
+#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
+#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
+#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
+#define GPMI_DEBUG2_RDN_TAP_OFFSET 0
+
+#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
+#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
+#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
+#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
+
+#endif /* __REGS_GPMI_H__ */
--
1.7.5.4