From mboxrd@z Thu Jan  1 00:00:00 1970
From: Graeme Russ <graeme.russ@gmail.com>
Date: Tue, 20 Sep 2011 20:45:14 +1000
Subject: [U-Boot] [PATCH] arm: add 64-64 bit divider
In-Reply-To: <20110907211411.2C91C140875D@gemini.denx.de>
References: <1314787130-1043-1-git-send-email-clchiou@chromium.org>	<20110831200355.A71D018D30CE@gemini.denx.de>	<CANJuy2+BB7tA70vHoTq3LJA-o4ymGCSdP9PnFzrx-uWret7nqQ@mail.gmail.com>
	<20110907211411.2C91C140875D@gemini.denx.de>
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Hi Wolfgang,

On 08/09/11 07:14, Wolfgang Denk wrote:
> Dear Che-liang Chiou,
> 
> In message <CANJuy2+BB7tA70vHoTq3LJA-o4ymGCSdP9PnFzrx-uWret7nqQ@mail.gmail.com> you wrote:
>>
>> So I guess we can agree that a 64-bit divider is feature that is nice
>> to have, and we should decide:
>> * Do we need a 64-64 bit divider or a 64-32 bit one?
>> * Do we write it in C or assembly?
> 
> The situation is simple:  there is no code in U-Boot that needs this
> feature, and we try to avoid adding dead code.
> 
> If you don;t have a use case at hand that actually requires this, then
> please let's drop it.

You'll laugh at this - the Intel High Performance Event Timers (HPET) are
defined to a resolution of femto-seconds and you end up with code in
get_timer() like:

	u32 count_low;
	u32 count_high;
	u32 fs_per_tick;
	u64 ticks;
	u64 fs;
	u32 ms;

	count_low = readl(&hpet_registers->main_count_low);
	count_high = readl(&hpet_registers->main_count_high);
	fs_per_tick = readl(&hpet_registers->counter_clk_period);

	ticks = ((u64)count_high << 32) | ((u64)count_low);
	fs = fs_per_tick * ticks;
	ms = (u32)lldiv(ticks, 1000000000000);

But I can right shift both divisor and dividend by 12 bits without loosing
any significant precision which turns it into:

	ms = (u32)lldiv(ticks >> 12, 244140625);

So I almost needed a 64 bit divisor.

Regards,

Graeme