From mboxrd@z Thu Jan  1 00:00:00 1970
From: Sergei Shtylyov <sshtylyov@mvista.com>
Date: Wed, 28 Sep 2011 12:58:45 +0400
Subject: [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
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References: <E1R8VUh-0000hD-CK@rhodium.platinum.guralp.com>
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To: u-boot@lists.denx.de

Hello.

On 26-09-2011 20:02, Laurence Withers wrote:

> In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
> on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
> This allows 1-bit hardware ECC to work with chip select other than CS2.

> Note this now matches the usage in nand_davinci_enable_hwecc(), which
> already had the correct handling, and allows refactoring to a single
> function encapsulating the register read.

> Without this fix, writing NAND pages to a chip not wired to CS2 would
> result in in the ECC calculation always returning FFFFFF for each
> 512-byte segment, and reading back a correctly written page (one with
> ECC intact) would always fail. With this fix, the ECC is written and
> verified correctly.

    You need to sign off your patch. Add this line to the changelog:

Signed-off-by: Laurence Withers <lwithers@guralp.com>

WBR, Sergei