* [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
@ 2011-09-26 16:02 Laurence Withers
2011-09-26 16:02 ` [U-Boot] [PATCH v2] " Laurence Withers
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Laurence Withers @ 2011-09-26 16:02 UTC (permalink / raw)
To: u-boot
In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
---
drivers/mtd/nand/davinci_nand.c | 26 +++++++++++++-------------
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c..e8506dd 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
#ifdef CONFIG_SYS_NAND_HW_ECC
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
+{
+ u_int32_t ecc = 0;
+
+ ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
+ CONFIG_SYS_NAND_CS - 2]));
+
+ return ecc;
+}
+
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
u_int32_t val;
- (void)__raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ /* reading the ECC result register resets the ECC calculation */
+ nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
@@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
- u_int32_t ecc = 0;
-
- ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
-
- return ecc;
-}
-
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
u_int32_t tmp;
- const int region = 1;
- tmp = nand_davinci_readecc(mtd, region);
+ tmp = nand_davinci_readecc(mtd);
/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
--
1.7.2.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* [U-Boot] [PATCH v2] NAND: davinci: choose correct 1-bit h/w ECC reg
2011-09-26 16:02 [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg Laurence Withers
@ 2011-09-26 16:02 ` Laurence Withers
2011-10-10 13:45 ` Laurence Withers
2011-10-10 20:29 ` Scott Wood
2011-09-26 16:02 ` [U-Boot] [PATCH] " Laurence Withers
2011-09-28 8:58 ` Sergei Shtylyov
2 siblings, 2 replies; 7+ messages in thread
From: Laurence Withers @ 2011-09-26 16:02 UTC (permalink / raw)
To: u-boot
In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
---
Changes for v2:
Add Signed-off-by to commit message.
---
drivers/mtd/nand/davinci_nand.c | 26 +++++++++++++-------------
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c..e8506dd 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
#ifdef CONFIG_SYS_NAND_HW_ECC
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
+{
+ u_int32_t ecc = 0;
+
+ ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
+ CONFIG_SYS_NAND_CS - 2]));
+
+ return ecc;
+}
+
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
u_int32_t val;
- (void)__raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ /* reading the ECC result register resets the ECC calculation */
+ nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
@@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
- u_int32_t ecc = 0;
-
- ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
-
- return ecc;
-}
-
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
u_int32_t tmp;
- const int region = 1;
- tmp = nand_davinci_readecc(mtd, region);
+ tmp = nand_davinci_readecc(mtd);
/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
--
1.7.2.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* [U-Boot] [PATCH v2] NAND: davinci: choose correct 1-bit h/w ECC reg
2011-09-26 16:02 ` [U-Boot] [PATCH v2] " Laurence Withers
@ 2011-10-10 13:45 ` Laurence Withers
2011-10-10 20:29 ` Scott Wood
1 sibling, 0 replies; 7+ messages in thread
From: Laurence Withers @ 2011-10-10 13:45 UTC (permalink / raw)
To: u-boot
On Mon, Sep 26, 2011 at 04:02:30PM +0000, Laurence Withers wrote:
> In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
> on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
> This allows 1-bit hardware ECC to work with chip select other than CS2.
>
> Note this now matches the usage in nand_davinci_enable_hwecc(), which
> already had the correct handling, and allows refactoring to a single
> function encapsulating the register read.
>
> Without this fix, writing NAND pages to a chip not wired to CS2 would
> result in in the ECC calculation always returning FFFFFF for each
> 512-byte segment, and reading back a correctly written page (one with
> ECC intact) would always fail. With this fix, the ECC is written and
> verified correctly.
>
> Signed-off-by: Laurence Withers <lwithers@guralp.com>
Does anybody have any comments on this bugfix? If not, can it be accepted?
Many thanks, and bye for now,
--
Laurence Withers, <lwithers@guralp.com> http://www.guralp.com/
Direct tel:+447753988197 or tel:+443333408643 Software Engineer
General support queries: <support@guralp.com> CMG-DCM CMG-EAM CMG-NAM
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v2] NAND: davinci: choose correct 1-bit h/w ECC reg
2011-09-26 16:02 ` [U-Boot] [PATCH v2] " Laurence Withers
2011-10-10 13:45 ` Laurence Withers
@ 2011-10-10 20:29 ` Scott Wood
1 sibling, 0 replies; 7+ messages in thread
From: Scott Wood @ 2011-10-10 20:29 UTC (permalink / raw)
To: u-boot
On 09/26/2011 11:02 AM, Laurence Withers wrote:
> In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
> on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
> This allows 1-bit hardware ECC to work with chip select other than CS2.
>
> Note this now matches the usage in nand_davinci_enable_hwecc(), which
> already had the correct handling, and allows refactoring to a single
> function encapsulating the register read.
>
> Without this fix, writing NAND pages to a chip not wired to CS2 would
> result in in the ECC calculation always returning FFFFFF for each
> 512-byte segment, and reading back a correctly written page (one with
> ECC intact) would always fail. With this fix, the ECC is written and
> verified correctly.
>
> Signed-off-by: Laurence Withers <lwithers@guralp.com>
> ---
> Changes for v2:
> Add Signed-off-by to commit message.
> ---
> drivers/mtd/nand/davinci_nand.c | 26 +++++++++++++-------------
> 1 files changed, 13 insertions(+), 13 deletions(-)
Applied to u-boot-nand-flash
-Scott
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
2011-09-26 16:02 [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg Laurence Withers
2011-09-26 16:02 ` [U-Boot] [PATCH v2] " Laurence Withers
@ 2011-09-26 16:02 ` Laurence Withers
2011-09-28 8:58 ` Sergei Shtylyov
2 siblings, 0 replies; 7+ messages in thread
From: Laurence Withers @ 2011-09-26 16:02 UTC (permalink / raw)
To: u-boot
In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
---
Changes for v2:
Add Signed-off-by to commit message.
---
drivers/mtd/nand/davinci_nand.c | 26 +++++++++++++-------------
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c..e8506dd 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
#ifdef CONFIG_SYS_NAND_HW_ECC
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
+{
+ u_int32_t ecc = 0;
+
+ ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
+ CONFIG_SYS_NAND_CS - 2]));
+
+ return ecc;
+}
+
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
u_int32_t val;
- (void)__raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ /* reading the ECC result register resets the ECC calculation */
+ nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
@@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
- u_int32_t ecc = 0;
-
- ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
-
- return ecc;
-}
-
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
u_int32_t tmp;
- const int region = 1;
- tmp = nand_davinci_readecc(mtd, region);
+ tmp = nand_davinci_readecc(mtd);
/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
--
1.7.2.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
2011-09-26 16:02 [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg Laurence Withers
2011-09-26 16:02 ` [U-Boot] [PATCH v2] " Laurence Withers
2011-09-26 16:02 ` [U-Boot] [PATCH] " Laurence Withers
@ 2011-09-28 8:58 ` Sergei Shtylyov
2011-09-29 10:18 ` Laurence Withers
2 siblings, 1 reply; 7+ messages in thread
From: Sergei Shtylyov @ 2011-09-28 8:58 UTC (permalink / raw)
To: u-boot
Hello.
On 26-09-2011 20:02, Laurence Withers wrote:
> In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
> on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
> This allows 1-bit hardware ECC to work with chip select other than CS2.
> Note this now matches the usage in nand_davinci_enable_hwecc(), which
> already had the correct handling, and allows refactoring to a single
> function encapsulating the register read.
> Without this fix, writing NAND pages to a chip not wired to CS2 would
> result in in the ECC calculation always returning FFFFFF for each
> 512-byte segment, and reading back a correctly written page (one with
> ECC intact) would always fail. With this fix, the ECC is written and
> verified correctly.
You need to sign off your patch. Add this line to the changelog:
Signed-off-by: Laurence Withers <lwithers@guralp.com>
WBR, Sergei
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
2011-09-28 8:58 ` Sergei Shtylyov
@ 2011-09-29 10:18 ` Laurence Withers
0 siblings, 0 replies; 7+ messages in thread
From: Laurence Withers @ 2011-09-29 10:18 UTC (permalink / raw)
To: u-boot
On Wed, Sep 28, 2011 at 12:58:45PM +0400, Sergei Shtylyov wrote:
> You need to sign off your patch. Add this line to the changelog:
>
> Signed-off-by: Laurence Withers <lwithers@guralp.com>
Thanks, I have reposted v2. Please ignore the posting with the unaltered
subject line; I only realised after sending that I had forgotten it.
Bye for now,
--
Laurence Withers, <lwithers@guralp.com> http://www.guralp.com/
Direct tel:+447753988197 or tel:+443333408643 Software Engineer
General support queries: <support@guralp.com> CMG-DCM CMG-EAM CMG-NAM
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2011-10-10 20:29 UTC | newest]
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2011-09-26 16:02 [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg Laurence Withers
2011-09-26 16:02 ` [U-Boot] [PATCH v2] " Laurence Withers
2011-10-10 13:45 ` Laurence Withers
2011-10-10 20:29 ` Scott Wood
2011-09-26 16:02 ` [U-Boot] [PATCH] " Laurence Withers
2011-09-28 8:58 ` Sergei Shtylyov
2011-09-29 10:18 ` Laurence Withers
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