[U-Boot] [PATCH V2] mx31: provide readable WEIM CS accessor

Helmut Raiger
2011-09-29T12:19:09Z

mxc_setup_weimcs() and some macros are added to support the setup
for i.MX31 WEIM chip selects. As a compromise between verbosity
and readability an ASCII-art'ish bit comment is used instead of
bitfields.
All i.MX31 boards have been patched to use this approach using a
helper program to verify the changes.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
---
V2:
added sys_proto.h for mx31
introduced mxc_setup_weimcs(), which is SOC independent
not inlined any more (codesize increased by 60-90 bytes)
---
arch/arm/include/asm/arch-mx31/imx-regs.h | 26 +++++++-
arch/arm/include/asm/arch-mx31/sys_proto.h | 35 +++++++++++
board/davedenx/qong/qong.c | 87 ++++++++++-----------------
board/freescale/mx31ads/mx31ads.c | 15 ++++-
board/freescale/mx31pdk/mx31pdk.c | 14 ++++-
board/imx31_phycore/imx31_phycore.c | 41 ++++++++++---
board/logicpd/imx31_litekit/imx31_litekit.c | 28 +++++++--
7 files changed, 167 insertions(+), 79 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx31/sys_proto.h

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 2064870..d631a10 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -534,10 +534,30 @@ enum iomux_pins {
#define ESDCTL_BL(x) ((x) << 7)
#define ESDCTL_PRCT(x) ((x) << 0)

+/* 13 fields of the upper CS control register */
+#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
+ cnc, wsc, ew, wws, edc) \
+ ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
+ (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
+ (wws) << 4 | (edc) << 0)
+/* 12 fields of the lower CS control register */
+#define CSCR_L(oea, oen, ebwa, ebwn, \
+ csa, ebc, dsz, csn, psr, cre, wrap, csen) \
+ ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
+ (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
+ (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
+/* 14 fields of the additional CS control register */
+#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
+ wwu, age, cnc2, fce) \
+ ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
+ (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
+ (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
+ (age) << 2 | (cnc2) << 1 | (fce) << 0)
+
#define WEIM_BASE 0xb8002000
-#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
-#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
-#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
+#define WEIM_CSCR_U(x) (WEIM_BASE + (x) * 0x10)
+#define WEIM_CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
+#define WEIM_CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)

#define IOMUXC_BASE 0x43FAC000
#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h
new file mode 100644
index 0000000..7600303
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx31/sys_proto.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2011
+ * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+struct mxc_weimcs {
+ u32 upper;
+ u32 lower;
+ u32 additional;
+};
+
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
+
+#endif
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 99432ed..b9133bc 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -25,7 +25,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
#include <nand.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
@@ -61,11 +61,17 @@ static void qong_fpga_reset(void)
int board_early_init_f (void)
{
#ifdef CONFIG_QONG_FPGA
- /* CS1: FPGA/Network Controller/GPIO */
- /* 16-bit, no DTACK */
- __REG(CSCR_U(1)) = 0x00000A01;
- __REG(CSCR_L(1)) = 0x20040501;
- __REG(CSCR_A(1)) = 0x04020C00;
+ /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
+ static const struct mxc_weimcs cs1 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(1, &cs1);

/* setup pins for FPGA */
mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
@@ -146,50 +152,16 @@ int board_init (void)
/* Chip selects */
/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
- __REG(CSCR_U(0)) = ((0 << 31) | /* SP */
- (0 << 30) | /* WP */
- (0 << 28) | /* BCD */
- (0 << 24) | /* BCS */
- (0 << 22) | /* PSZ */
- (0 << 21) | /* PME */
- (0 << 20) | /* SYNC */
- (0 << 16) | /* DOL */
- (3 << 14) | /* CNC */
- (21 << 8) | /* WSC */
- (0 << 7) | /* EW */
- (0 << 4) | /* WWS */
- (6 << 0) /* EDC */
- );
-
- __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
- (1 << 24) | /* OEN */
- (3 << 20) | /* EBWA */
- (3 << 16) | /* EBWN */
- (1 << 12) | /* CSA */
- (1 << 11) | /* EBC */
- (5 << 8) | /* DSZ */
- (1 << 4) | /* CSN */
- (0 << 3) | /* PSR */
- (0 << 2) | /* CRE */
- (0 << 1) | /* WRAP */
- (1 << 0) /* CSEN */
- );
-
- __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
- (1 << 24) | /* EBRN */
- (2 << 20) | /* RWA */
- (2 << 16) | /* RWN */
- (0 << 15) | /* MUM */
- (0 << 13) | /* LAH */
- (2 << 10) | /* LBN */
- (0 << 8) | /* LBA */
- (0 << 6) | /* DWW */
- (0 << 4) | /* DCT */
- (0 << 3) | /* WWU */
- (0 << 2) | /* AGE */
- (0 << 1) | /* CNC2 */
- (0 << 0) /* FCE */
- );
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);

/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_QONG;
@@ -247,11 +219,18 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
static void board_nand_setup(void)
{
-
/* CS3: NAND 8-bit */
- __REG(CSCR_U(3)) = 0x00004f00;
- __REG(CSCR_L(3)) = 0x20013b31;
- __REG(CSCR_A(3)) = 0x00020800;
+ static const struct mxc_weimcs cs3 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(3, &cs3);
+
__REG(IOMUXC_GPR) |= 1 << 13;

mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
index 7637c92..6cf3a8a 100644
--- a/board/freescale/mx31ads/mx31ads.c
+++ b/board/freescale/mx31ads/mx31ads.c
@@ -22,9 +22,9 @@

#include <common.h>
#include <netdev.h>
-#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -54,9 +54,16 @@ int board_early_init_f(void)
* the only non-zero field "Wait State Control" is set to half the
* default value.
*/
- __REG(CSCR_U(0)) = 0x00000f00;
- __REG(CSCR_L(0)) = 0x10000D03;
- __REG(CSCR_A(0)) = 0x00720900;
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);

/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index f6e190a..1bcf1fb 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -28,6 +28,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
#include <watchdog.h>

DECLARE_GLOBAL_DATA_PTR;
@@ -56,9 +57,16 @@ void dram_init_banksize(void)
int board_early_init_f(void)
{
/* CS5: CPLD incl. network controller */
- __REG(CSCR_U(5)) = 0x0000d843;
- __REG(CSCR_L(5)) = 0x22252521;
- __REG(CSCR_A(5)) = 0x22220a00;
+ static const struct mxc_weimcs cs5 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(5, &cs5);

/* Setup UART1 and SPI2 pins */
mx31_uart1_hw_init();
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 773900e..a697e47 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -27,6 +27,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -49,17 +50,39 @@ int board_init(void)

int board_early_init_f(void)
{
- __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
- __REG(CSCR_L(0)) = 0x10000d03;
- __REG(CSCR_A(0)) = 0x00720900;
+ /* CS0: Nor Flash */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
+ };
+
+ /* CS1: Network Controller */
+ static const struct mxc_weimcs cs1 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };

- __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
- __REG(CSCR_L(1)) = 0x444a4541;
- __REG(CSCR_A(1)) = 0x44443302;
+ /* CS4: SRAM */
+ static const struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
+ };

- __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
- __REG(CSCR_L(4)) = 0x22252521;
- __REG(CSCR_A(4)) = 0x22220a00;
+ mxc_setup_weimcs(0, &cs0);
+ mxc_setup_weimcs(1, &cs1);
+ mxc_setup_weimcs(4, &cs4);

/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
index 09cc9c5..0615215 100644
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -26,6 +26,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -45,13 +46,28 @@ void dram_init_banksize(void)

int board_early_init_f(void)
{
- __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
- __REG(CSCR_L(0)) = 0xa0330d01;
- __REG(CSCR_A(0)) = 0x00220800;
+ /* CS0: Nor Flash */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };

- __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
- __REG(CSCR_L(4)) = 0x444a4541;
- __REG(CSCR_A(4)) = 0x44443302;
+ /* CS4: Network Controller */
+ static const struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
+ mxc_setup_weimcs(4, &cs4);

/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
--
1.7.4.4

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