* [U-Boot] [PATCH 02/12] Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 12:06 ` Laurence Withers
2011-10-05 9:43 ` [U-Boot] [PATCH 03/12] Davinci: ea20: Add NAND support Stefano Babic
` (11 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
From: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: dzu at denx.de
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
arch/arm/include/asm/arch-davinci/hardware.h | 4 +++
board/davinci/ea20/ea20.c | 30 +++++++++++++++++++++++++-
2 files changed, 33 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 2063c66..59aea5e 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -171,6 +171,10 @@ typedef volatile unsigned int * dv_reg_p;
#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
+#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
+#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
+#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
+#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 4e4107a..3b636ff 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -35,6 +35,7 @@
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
+#include <asm/arch/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -90,6 +91,12 @@ const struct pinmux_config nand_pins[] = {
};
#endif
+const struct pinmux_config gpio_pins[] = {
+ { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
+ { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
+ { pinmux(13), 8, 3 } /* GPIO6[12] U0_SW1 on EA20-00101_2*/
+};
+
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
@@ -110,11 +117,32 @@ static const struct lpsc_resource lpsc[] = {
int board_init(void)
{
+ struct davinci_gpio *gpio6_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
+
+ /* PinMux for GPIO */
+ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+ return 1;
+
+ /* Set the RESETOUTn low */
+ writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
+
+ /* Set U0_SW0 low for UART0 as console*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
+
+ /* Set U0_SW1 low for UART0 as console*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
+
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
-
#ifdef CONFIG_NAND_DAVINCI
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 02/12] Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
2011-10-05 9:43 ` [U-Boot] [PATCH 02/12] Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console Stefano Babic
@ 2011-10-05 12:06 ` Laurence Withers
2011-10-05 13:00 ` Stefano Babic
0 siblings, 1 reply; 28+ messages in thread
From: Laurence Withers @ 2011-10-05 12:06 UTC (permalink / raw)
To: u-boot
On Wed, Oct 05, 2011 at 11:43:29AM +0200, Stefano Babic wrote:
> From: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
>
> Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> CC: dzu at denx.de
> CC: Sandeep Paulraj <s-paulraj@ti.com>
> ---
> arch/arm/include/asm/arch-davinci/hardware.h | 4 +++
> board/davinci/ea20/ea20.c | 30 +++++++++++++++++++++++++-
> 2 files changed, 33 insertions(+), 1 deletions(-)
There are generic GPIO functions (asm/gpio.h) for DaVinci; you should
probably use those instead of directly programming the registers.
Bye for now,
--
Laurence Withers, <lwithers@guralp.com> http://www.guralp.com/
Direct tel:+447753988197 or tel:+443333408643 Software Engineer
General support queries: <support@guralp.com> CMG-DCM CMG-EAM CMG-NAM
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 02/12] Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
2011-10-05 12:06 ` Laurence Withers
@ 2011-10-05 13:00 ` Stefano Babic
0 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 13:00 UTC (permalink / raw)
To: u-boot
On 10/05/2011 02:06 PM, Laurence Withers wrote:
> On Wed, Oct 05, 2011 at 11:43:29AM +0200, Stefano Babic wrote:
>> From: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
>>
>> Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>> CC: dzu at denx.de
>> CC: Sandeep Paulraj <s-paulraj@ti.com>
>> ---
>> arch/arm/include/asm/arch-davinci/hardware.h | 4 +++
>> board/davinci/ea20/ea20.c | 30 +++++++++++++++++++++++++-
>> 2 files changed, 33 insertions(+), 1 deletions(-)
>
> There are generic GPIO functions (asm/gpio.h) for DaVinci; you should
> probably use those instead of directly programming the registers.
Right. Then I prepare an additional patch to clean up all direct access
to gpio registers to this files and I add to this patchset.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 03/12] Davinci: ea20: Add NAND support
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 02/12] Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 04/12] Davinci: ea20: Add early init to get early output from console Stefano Babic
` (10 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
CC: Scott Wood <scottwood@freescale.com>
---
board/davinci/ea20/ea20.c | 35 ++++++++++++++++++-----------------
include/configs/ea20.h | 20 +++++++++++++++++---
2 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 3b636ff..f9ad121 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -74,20 +74,21 @@ static const struct pinmux_config emac_pins[] = {
#ifdef CONFIG_NAND_DAVINCI
const struct pinmux_config nand_pins[] = {
- { pinmux(7), 1, 1 },
- { pinmux(7), 1, 2 },
- { pinmux(7), 1, 4 },
- { pinmux(7), 1, 5 },
- { pinmux(9), 1, 0 },
- { pinmux(9), 1, 1 },
- { pinmux(9), 1, 2 },
- { pinmux(9), 1, 3 },
- { pinmux(9), 1, 4 },
- { pinmux(9), 1, 5 },
- { pinmux(9), 1, 6 },
- { pinmux(9), 1, 7 },
- { pinmux(12), 1, 5 },
- { pinmux(12), 1, 6 }
+ { pinmux(7), 1, 0}, /* CS2 */
+ { pinmux(7), 0, 1}, /* CS3 in three state*/
+ { pinmux(7), 1, 4 }, /* EMA_WE */
+ { pinmux(7), 1, 5 }, /* EMA_OE */
+ { pinmux(9), 1, 0 }, /* EMA_D[7] */
+ { pinmux(9), 1, 1 }, /* EMA_D[6] */
+ { pinmux(9), 1, 2 }, /* EMA_D[5] */
+ { pinmux(9), 1, 3 }, /* EMA_D[4] */
+ { pinmux(9), 1, 4 }, /* EMA_D[3] */
+ { pinmux(9), 1, 5 }, /* EMA_D[2] */
+ { pinmux(9), 1, 6 }, /* EMA_D[1] */
+ { pinmux(9), 1, 7 }, /* EMA_D[0] */
+ { pinmux(12), 1, 5 }, /* EMA_A[2] */
+ { pinmux(12), 1, 6 }, /* EMA_A[1] */
+ { pinmux(6), 1, 0 } /* EMA_CLK */
};
#endif
@@ -143,20 +144,20 @@ int board_init(void)
irq_init();
#endif
-#ifdef CONFIG_NAND_DAVINCI
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
+#ifdef CONFIG_NAND_DAVINCI
writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(0) |
DAVINCI_ABCR_ASIZE_8BIT),
- &davinci_emif_regs->ab2cr); /* CS3 */
+ &davinci_emif_regs->ab1cr); /* CS2 */
#endif
/* arch number of the board */
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 601990a..2a7f531 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -28,6 +28,7 @@
*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_USE_SPIFLASH
+#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
/*
@@ -101,7 +102,7 @@
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#define CONFIG_SYS_NO_FLASH
#endif
@@ -153,7 +154,8 @@
#undef CONFIG_CMD_PING
#endif
-#ifdef CONFIG_USE_NAND
+/* NAND Setup */
+#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
@@ -165,8 +167,20 @@
#define CONFIG_RBTREE
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
+
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
+/* SPI Flash */
#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
@@ -175,7 +189,7 @@
#define CONFIG_CMD_SAVEENV
#endif
-#if !defined(CONFIG_USE_NAND) && \
+#if !defined(CONFIG_SYS_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 04/12] Davinci: ea20: Add early init to get early output from console
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 02/12] Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 03/12] Davinci: ea20: Add NAND support Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 05/12] Davinci: ea20: Add default U-Boot environment Stefano Babic
` (9 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
Use board_early_init_f so that the full boot log output can be displayed.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
board/davinci/ea20/ea20.c | 18 +++++++++++-------
1 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index f9ad121..da9086a 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -116,7 +116,7 @@ static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_GPIO },
};
-int board_init(void)
+int board_early_init_f(void)
{
struct davinci_gpio *gpio6_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
@@ -160,12 +160,6 @@ int board_init(void)
&davinci_emif_regs->ab1cr); /* CS2 */
#endif
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_EA20;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
@@ -201,6 +195,16 @@ int board_init(void)
return 0;
}
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ return 0;
+}
#ifdef CONFIG_DRIVER_TI_EMAC
/*
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 05/12] Davinci: ea20: Add default U-Boot environment
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (2 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 04/12] Davinci: ea20: Add early init to get early output from console Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 06/12] Davinci: ea20: add gpio for keeping power on in board_late_init Stefano Babic
` (8 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
include/configs/ea20.h | 80 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 80 insertions(+), 0 deletions(-)
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 2a7f531..7e0d833 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -30,6 +30,7 @@
#define CONFIG_USE_SPIFLASH
#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOARD_EARLY_INIT_F
/*
* SoC Configuration
@@ -203,4 +204,83 @@
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+
+#define CONFIG_HOSTNAME ea20
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "as=3\0" \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "rfsbargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rfsbpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "mtdids=nand0=davinci_nand.0\0" \
+ "mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel)," \
+ "8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0" \
+ "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
+ "ubi.mtd=${as} root=ubi0:rootfs\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=${consoledev},${baudrate}n8\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
+ "consoledev=ttyS0\0" \
+ "loadaddr=c0000014\0" \
+ "memory=32M\0" \
+ "kernel_addr_r=c0700000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run rfsbargs addip addtty addmtd addmisc addmem; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "ubifsload ${kernel_addr_r} /boot/uImage;" \
+ "ubifsumount; run nandargs addip addtty " \
+ "addmtd addmisc addmem;bootm ${kernel_addr_r}\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load_magic=if sf probe 0;then sf " \
+ "read c0000000 0x10000 0x60000;fi\0" \
+ "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "if ubifsload c0000014 /boot/u-boot.bin;" \
+ "then mw c0000008 ${filesize};else echo Error reading " \
+ "u-boot from nand!;fi\0" \
+ "load_net=if sf probe 0;then sf read c0000000 0x10000 0x60000;" \
+ "tftp c0000014 ${u-boot};" \
+ "mw c0000008 ${filesize};" \
+ "fi\0" \
+ "upd=if sf probe 0;then sf erase 10000 60000;" \
+ "sf write c0000000 10000 60000;" \
+ "fi\0" \
+ "ubootupd_net=if run load_net;then echo Updating u-boot;" \
+ "if run upd; then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
+ "bootcmd=run net_nfs\0"
+
#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 06/12] Davinci: ea20: add gpio for keeping power on in board_late_init
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (3 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 05/12] Davinci: ea20: Add default U-Boot environment Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 07/12] Davinci: ea20: add gpios for LCD backlight control Stefano Babic
` (7 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
From: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
The pin called HALTEN drives a transistor to operate the supply
voltage. After HALTEN is high, the user can release the power
switch button and the device will stay powered on.
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
CC: sbabic at denx.de
CC: dzu at denx.de
---
board/davinci/ea20/ea20.c | 25 +++++++++++++++++++++++++
include/configs/ea20.h | 1 +
2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index da9086a..1a57baf 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -98,6 +98,10 @@ const struct pinmux_config gpio_pins[] = {
{ pinmux(13), 8, 3 } /* GPIO6[12] U0_SW1 on EA20-00101_2*/
};
+const struct pinmux_config halten_pin[] = {
+ { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */
+};
+
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
@@ -205,6 +209,27 @@ int board_init(void)
return 0;
}
+
+#ifdef BOARD_LATE_INIT
+
+int board_late_init(void)
+{
+ struct davinci_gpio *gpio8_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK8;
+
+ /* PinMux for HALTEN */
+ if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
+ return 1;
+
+ /* Set HALTEN to high */
+ writel((readl(&gpio8_base->set_data) | (1 << 6)),
+ &gpio8_base->set_data);
+ writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir);
+
+ return 0;
+}
+#endif /* BOARD_LATE_INIT */
+
#ifdef CONFIG_DRIVER_TI_EMAC
/*
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 7e0d833..7c9e4da 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -31,6 +31,7 @@
#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOARD_EARLY_INIT_F
+#define BOARD_LATE_INIT
/*
* SoC Configuration
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 07/12] Davinci: ea20: add gpios for LCD backlight control
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (4 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 06/12] Davinci: ea20: add gpio for keeping power on in board_late_init Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 08/12] ARM: Davinci: added missing registers to hardware.h Stefano Babic
` (6 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
From: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
board/davinci/ea20/ea20.c | 14 +++++++++++++-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 1a57baf..c28d8df 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -95,7 +95,9 @@ const struct pinmux_config nand_pins[] = {
const struct pinmux_config gpio_pins[] = {
{ pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
{ pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
- { pinmux(13), 8, 3 } /* GPIO6[12] U0_SW1 on EA20-00101_2*/
+ { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
+ { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */
+ { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/
};
const struct pinmux_config halten_pin[] = {
@@ -144,6 +146,16 @@ int board_early_init_f(void)
&gpio6_base->set_data);
writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
+ /* Set LCD_B_PWR low to power down LCD Backlight*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 6)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir);
+
+ /* Set DISP_ON low to disable LCD output*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 1)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir);
+
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 08/12] ARM: Davinci: added missing registers to hardware.h
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (5 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 07/12] Davinci: ea20: add gpios for LCD backlight control Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx Stefano Babic
` (5 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
The hardware base address for ther LCD configuration
registers is missing, as well as some syscfg registers.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
arch/arm/include/asm/arch-davinci/hardware.h | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 59aea5e..9fdb167 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -157,6 +157,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
+#define DAVINCI_LCD_CNTL_BASE 0x01e13000
#define DAVINCI_L3CBARAM_BASE 0x80000000
#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
@@ -435,7 +436,8 @@ struct davinci_syscfg_regs {
dv_reg rsvd[13];
dv_reg kick0;
dv_reg kick1;
- dv_reg rsvd1[56];
+ dv_reg rsvd1[53];
+ dv_reg mstpri[3];
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (6 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 08/12] ARM: Davinci: added missing registers to hardware.h Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-06 22:14 ` Anatolij Gustschin
2011-10-06 22:32 ` Wolfgang Denk
2011-10-05 9:43 ` [U-Boot] [PATCH 10/12] Davinci: ea20: added video support Stefano Babic
` (4 subsequent siblings)
12 siblings, 2 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
The patch is a port of the Linux driver da8xx-fb.c used
on davinci da8xx and OMAP-L138 boards.
Last commit seen on this driver used as base
for porting is 1db41e032d563eb47deab40dc5595be306b143ba
(video: da8xx-fb: fix section mismatch warning)
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
---
arch/arm/include/asm/arch-davinci/da8xx-fb.h | 122 ++++
drivers/video/Makefile | 1 +
drivers/video/da8xx-fb.c | 846 ++++++++++++++++++++++++++
3 files changed, 969 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-davinci/da8xx-fb.h
create mode 100644 drivers/video/da8xx-fb.c
diff --git a/arch/arm/include/asm/arch-davinci/da8xx-fb.h b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
new file mode 100644
index 0000000..88613a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
@@ -0,0 +1,122 @@
+/*
+ * Header file for TI DA8XX LCD controller platform data.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef DA8XX_FB_H
+#define DA8XX_FB_H
+
+enum panel_type {
+ QVGA = 0
+};
+
+enum panel_shade {
+ MONOCHROME = 0,
+ COLOR_ACTIVE,
+ COLOR_PASSIVE,
+};
+
+enum raster_load_mode {
+ LOAD_DATA = 1,
+ LOAD_PALETTE,
+};
+
+struct display_panel {
+ enum panel_type panel_type; /* QVGA */
+ int max_bpp;
+ int min_bpp;
+ enum panel_shade panel_shade;
+};
+
+struct da8xx_panel {
+ const char name[25]; /* Full name <vendor>_<model> */
+ unsigned short width;
+ unsigned short height;
+ int hfp; /* Horizontal front porch */
+ int hbp; /* Horizontal back porch */
+ int hsw; /* Horizontal Sync Pulse Width */
+ int vfp; /* Vertical front porch */
+ int vbp; /* Vertical back porch */
+ int vsw; /* Vertical Sync Pulse Width */
+ unsigned int pxl_clk; /* Pixel clock */
+ unsigned char invert_pxl_clk; /* Invert Pixel clock */
+};
+
+struct da8xx_lcdc_platform_data {
+ const char manu_name[10];
+ void *controller_data;
+ const char type[25];
+ void (*panel_power_ctrl)(int);
+};
+
+struct lcd_ctrl_config {
+ const struct display_panel *p_disp_panel;
+
+ /* AC Bias Pin Frequency */
+ int ac_bias;
+
+ /* AC Bias Pin Transitions per Interrupt */
+ int ac_bias_intrpt;
+
+ /* DMA burst size */
+ int dma_burst_sz;
+
+ /* Bits per pixel */
+ int bpp;
+
+ /* FIFO DMA Request Delay */
+ int fdd;
+
+ /* TFT Alternative Signal Mapping (Only for active) */
+ unsigned char tft_alt_mode;
+
+ /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
+ unsigned char stn_565_mode;
+
+ /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+ unsigned char mono_8bit_mode;
+
+ /* Invert line clock */
+ unsigned char invert_line_clock;
+
+ /* Invert frame clock */
+ unsigned char invert_frm_clock;
+
+ /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+ unsigned char sync_edge;
+
+ /* Horizontal and Vertical Sync: Control: 0=ignore */
+ unsigned char sync_ctrl;
+
+ /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+ unsigned char raster_order;
+};
+
+struct lcd_sync_arg {
+ int back_porch;
+ int front_porch;
+ int pulse_width;
+};
+
+#if 0
+/* ioctls */
+#define FBIOGET_CONTRAST _IOR('F', 1, int)
+#define FBIOPUT_CONTRAST _IOW('F', 2, int)
+#define FBIGET_BRIGHTNESS _IOR('F', 3, int)
+#define FBIPUT_BRIGHTNESS _IOW('F', 3, int)
+#define FBIGET_COLOR _IOR('F', 5, int)
+#define FBIPUT_COLOR _IOW('F', 6, int)
+#define FBIPUT_HSYNC _IOW('F', 9, int)
+#define FBIPUT_VSYNC _IOW('F', 10, int)
+#endif
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+
+#endif /* ifndef DA8XX_FB_H */
+
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 3790f91..7aafd8c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
+COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
new file mode 100644
index 0000000..bca9fb5
--- /dev/null
+++ b/drivers/video/da8xx-fb.c
@@ -0,0 +1,846 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include "videomodes.h"
+#include <asm/arch/da8xx-fb.h>
+
+#define DRIVER_NAME "da8xx_lcdc"
+
+/* LCD Status Register */
+#define LCD_END_OF_FRAME1 (1 << 9)
+#define LCD_END_OF_FRAME0 (1 << 8)
+#define LCD_PL_LOAD_DONE (1 << 6)
+#define LCD_FIFO_UNDERFLOW (1 << 5)
+#define LCD_SYNC_LOST (1 << 2)
+
+/* LCD DMA Control Register */
+#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
+#define LCD_DMA_BURST_1 0x0
+#define LCD_DMA_BURST_2 0x1
+#define LCD_DMA_BURST_4 0x2
+#define LCD_DMA_BURST_8 0x3
+#define LCD_DMA_BURST_16 0x4
+#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
+
+/* LCD Control Register */
+#define LCD_CLK_DIVISOR(x) ((x) << 8)
+#define LCD_RASTER_MODE 0x01
+
+/* LCD Raster Control Register */
+#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
+#define PALETTE_AND_DATA 0x00
+#define PALETTE_ONLY 0x01
+#define DATA_ONLY 0x02
+
+#define LCD_MONO_8BIT_MODE (1 << 9)
+#define LCD_RASTER_ORDER (1 << 8)
+#define LCD_TFT_MODE (1 << 7)
+#define LCD_UNDERFLOW_INT_ENA (1 << 6)
+#define LCD_PL_ENABLE (1 << 4)
+#define LCD_MONOCHROME_MODE (1 << 1)
+#define LCD_RASTER_ENABLE (1 << 0)
+#define LCD_TFT_ALT_ENABLE (1 << 23)
+#define LCD_STN_565_ENABLE (1 << 24)
+
+/* LCD Raster Timing 2 Register */
+#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
+#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
+#define LCD_SYNC_CTRL (1 << 25)
+#define LCD_SYNC_EDGE (1 << 24)
+#define LCD_INVERT_PIXEL_CLOCK (1 << 22)
+#define LCD_INVERT_LINE_CLOCK (1 << 21)
+#define LCD_INVERT_FRAME_CLOCK (1 << 20)
+
+/* LCD Block */
+struct da8xx_lcd_regs {
+ u32 revid;
+ u32 ctrl;
+ u32 stat;
+ u32 lidd_ctrl;
+ u32 lidd_cs0_conf;
+ u32 lidd_cs0_addr;
+ u32 lidd_cs0_data;
+ u32 lidd_cs1_conf;
+ u32 lidd_cs1_addr;
+ u32 lidd_cs1_data;
+ u32 raster_ctrl;
+ u32 raster_timing_0;
+ u32 raster_timing_1;
+ u32 raster_timing_2;
+ u32 raster_subpanel;
+ u32 reserved;
+ u32 dma_ctrl;
+ u32 dma_frm_buf_base_addr_0;
+ u32 dma_frm_buf_ceiling_addr_0;
+ u32 dma_frm_buf_base_addr_1;
+ u32 dma_frm_buf_ceiling_addr_1;
+};
+
+#define LCD_NUM_BUFFERS 1
+
+#define WSI_TIMEOUT 50
+#define PALETTE_SIZE 256
+#define LEFT_MARGIN 64
+#define RIGHT_MARGIN 64
+#define UPPER_MARGIN 32
+#define LOWER_MARGIN 32
+
+#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+static struct da8xx_lcd_regs *da8xx_fb_reg_base;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* graphics setup */
+static GraphicDevice gpanel;
+static const struct da8xx_panel *lcd_panel;
+static struct fb_info *da8xx_fb_info;
+static int bits_x_pixel;
+
+static inline unsigned int lcdc_read(u32 *addr)
+{
+ return (unsigned int)readl(addr);
+}
+
+static inline void lcdc_write(unsigned int val, u32 *addr)
+{
+ writel(val, addr);
+}
+
+struct da8xx_fb_par {
+ u32 p_palette_base;
+ unsigned char *v_palette_base;
+ dma_addr_t vram_phys;
+ unsigned long vram_size;
+ void *vram_virt;
+ unsigned int dma_start;
+ unsigned int dma_end;
+ struct clk *lcdc_clk;
+ int irq;
+ unsigned short pseudo_palette[16];
+ unsigned int palette_sz;
+ unsigned int pxl_clk;
+ int blank;
+ int vsync_flag;
+ int vsync_timeout;
+};
+
+
+/* Variable Screen Information */
+static struct fb_var_screeninfo da8xx_fb_var = {
+ .xoffset = 0,
+ .yoffset = 0,
+ .transp = {0, 0, 0},
+ .nonstd = 0,
+ .activate = 0,
+ .height = -1,
+ .width = -1,
+ .pixclock = 46666, /* 46us - AUO display */
+ .accel_flags = 0,
+ .left_margin = LEFT_MARGIN,
+ .right_margin = RIGHT_MARGIN,
+ .upper_margin = UPPER_MARGIN,
+ .lower_margin = LOWER_MARGIN,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_fix_screeninfo da8xx_fb_fix = {
+ .id = "DA8xx FB Drv",
+ .type = FB_TYPE_PACKED_PIXELS,
+ .type_aux = 0,
+ .visual = FB_VISUAL_PSEUDOCOLOR,
+ .xpanstep = 0,
+ .ypanstep = 1,
+ .ywrapstep = 0,
+ .accel = FB_ACCEL_NONE
+};
+
+static const struct display_panel disp_panel = {
+ QVGA,
+ 16,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 255,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+/* Enable the Raster Engine of the LCD Controller */
+static inline void lcd_enable_raster(void)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ if (!(reg & LCD_RASTER_ENABLE))
+ lcdc_write(reg | LCD_RASTER_ENABLE,
+ &da8xx_fb_reg_base->raster_ctrl);
+}
+
+/* Disable the Raster Engine of the LCD Controller */
+static inline void lcd_disable_raster(void)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ if (reg & LCD_RASTER_ENABLE)
+ lcdc_write(reg & ~LCD_RASTER_ENABLE,
+ &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+{
+ u32 start;
+ u32 end;
+ u32 reg_ras;
+ u32 reg_dma;
+
+ /* init reg to clear PLM (loading mode) fields */
+ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ reg_ras &= ~(3 << 20);
+
+ reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
+
+ if (load_mode == LOAD_DATA) {
+ start = par->dma_start;
+ end = par->dma_end;
+
+ reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
+ reg_dma |= LCD_END_OF_FRAME_INT_ENA;
+
+#if (LCD_NUM_BUFFERS == 2)
+ reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#else
+ reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#endif
+
+ } else if (load_mode == LOAD_PALETTE) {
+ start = par->p_palette_base;
+ end = start + par->palette_sz - 1;
+
+ reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+ reg_ras |= LCD_PL_ENABLE;
+
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ }
+
+ lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
+ lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+ /*
+ * The Raster enable bit must be set after all other control fields are
+ * set.
+ */
+ lcd_enable_raster();
+}
+
+/* Configure the Burst Size of DMA */
+static int lcd_cfg_dma(int burst_size)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
+ switch (burst_size) {
+ case 1:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+ break;
+ case 2:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+ break;
+ case 4:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+ break;
+ case 8:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+ break;
+ case 16:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+ break;
+ default:
+ return -EINVAL;
+ }
+ lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
+
+ return 0;
+}
+
+static void lcd_cfg_ac_bias(int period, int transitions_per_int)
+{
+ u32 reg;
+
+ /* Set the AC Bias Period and Number of Transisitons per Interrupt */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
+ reg |= LCD_AC_BIAS_FREQUENCY(period) |
+ LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+}
+
+static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+ int front_porch)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
+ reg |= ((back_porch & 0xff) << 24)
+ | ((front_porch & 0xff) << 16)
+ | ((pulse_width & 0x3f) << 10);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+}
+
+static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+ int front_porch)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
+ reg |= ((back_porch & 0xff) << 24)
+ | ((front_porch & 0xff) << 16)
+ | ((pulse_width & 0x3f) << 10);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+}
+
+static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
+ LCD_MONO_8BIT_MODE |
+ LCD_MONOCHROME_MODE);
+
+ switch (cfg->p_disp_panel->panel_shade) {
+ case MONOCHROME:
+ reg |= LCD_MONOCHROME_MODE;
+ if (cfg->mono_8bit_mode)
+ reg |= LCD_MONO_8BIT_MODE;
+ break;
+ case COLOR_ACTIVE:
+ reg |= LCD_TFT_MODE;
+ if (cfg->tft_alt_mode)
+ reg |= LCD_TFT_ALT_ENABLE;
+ break;
+
+ case COLOR_PASSIVE:
+ if (cfg->stn_565_mode)
+ reg |= LCD_STN_565_ENABLE;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ /* enable additional interrupts here */
+ reg |= LCD_UNDERFLOW_INT_ENA;
+
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
+
+ if (cfg->sync_ctrl)
+ reg |= LCD_SYNC_CTRL;
+ else
+ reg &= ~LCD_SYNC_CTRL;
+
+ if (cfg->sync_edge)
+ reg |= LCD_SYNC_EDGE;
+ else
+ reg &= ~LCD_SYNC_EDGE;
+
+ if (cfg->invert_line_clock)
+ reg |= LCD_INVERT_LINE_CLOCK;
+ else
+ reg &= ~LCD_INVERT_LINE_CLOCK;
+
+ if (cfg->invert_frm_clock)
+ reg |= LCD_INVERT_FRAME_CLOCK;
+ else
+ reg &= ~LCD_INVERT_FRAME_CLOCK;
+
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+
+ return 0;
+}
+
+static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
+ u32 bpp, u32 raster_order)
+{
+ u32 reg;
+
+ /* Set the Panel Width */
+ /* Pixels per line = (PPL + 1)*16 */
+ /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
+ width &= 0x3f0;
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
+ reg &= 0xfffffc00;
+ reg |= ((width >> 4) - 1) << 4;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+
+ /* Set the Panel Height */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
+ reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+
+ /* Set the Raster Order of the Frame Buffer */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
+ if (raster_order)
+ reg |= LCD_RASTER_ORDER;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+ switch (bpp) {
+ case 1:
+ case 2:
+ case 4:
+ case 16:
+ par->palette_sz = 16 * 2;
+ break;
+
+ case 8:
+ par->palette_sz = 256 * 2;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ struct da8xx_fb_par *par = info->par;
+ unsigned short *palette = (unsigned short *) par->v_palette_base;
+ u_short pal;
+ int update_hw = 0;
+
+ if (regno > 255)
+ return 1;
+
+ if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+ return 1;
+
+ if (info->var.bits_per_pixel == 8) {
+ red >>= 4;
+ green >>= 8;
+ blue >>= 12;
+
+ pal = (red & 0x0f00);
+ pal |= (green & 0x00f0);
+ pal |= (blue & 0x000f);
+
+ if (palette[regno] != pal) {
+ update_hw = 1;
+ palette[regno] = pal;
+ }
+ } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+ red >>= (16 - info->var.red.length);
+ red <<= info->var.red.offset;
+
+ green >>= (16 - info->var.green.length);
+ green <<= info->var.green.offset;
+
+ blue >>= (16 - info->var.blue.length);
+ blue <<= info->var.blue.offset;
+
+ par->pseudo_palette[regno] = red | green | blue;
+
+ if (palette[0] != 0x4000) {
+ update_hw = 1;
+ palette[0] = 0x4000;
+ }
+ }
+
+ /* Update the palette in the h/w as needed. */
+ if (update_hw)
+ lcd_blit(LOAD_PALETTE, par);
+
+ return 0;
+}
+
+static void lcd_reset(struct da8xx_fb_par *par)
+{
+ /* Disable the Raster if previously Enabled */
+ lcd_disable_raster();
+
+ /* DMA has to be disabled */
+ lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
+ lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
+{
+ unsigned int lcd_clk, div;
+
+ /* Get clock from sysclk2 */
+ lcd_clk = clk_get(2);
+
+ div = lcd_clk / par->pxl_clk;
+ debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
+ lcd_clk, div, par->pxl_clk);
+
+ /* Configure the LCD clock divisor. */
+ lcdc_write(LCD_CLK_DIVISOR(div) |
+ (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+}
+
+static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+ const struct da8xx_panel *panel)
+{
+ u32 bpp;
+ int ret = 0;
+
+ lcd_reset(par);
+
+ /* Calculate the divider */
+ lcd_calc_clk_divider(par);
+
+ if (panel->invert_pxl_clk)
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
+ LCD_INVERT_PIXEL_CLOCK),
+ &da8xx_fb_reg_base->raster_timing_2);
+ else
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
+ ~LCD_INVERT_PIXEL_CLOCK),
+ &da8xx_fb_reg_base->raster_timing_2);
+
+ /* Configure the DMA burst size. */
+ ret = lcd_cfg_dma(cfg->dma_burst_sz);
+ if (ret < 0)
+ return ret;
+
+ /* Configure the AC bias properties. */
+ lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
+
+ /* Configure the vertical and horizontal sync properties. */
+ lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
+ lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+
+ /* Configure for disply */
+ ret = lcd_cfg_display(cfg);
+ if (ret < 0)
+ return ret;
+
+ if (QVGA != cfg->p_disp_panel->panel_type)
+ return -EINVAL;
+
+ if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+ cfg->bpp >= cfg->p_disp_panel->min_bpp)
+ bpp = cfg->bpp;
+ else
+ bpp = cfg->p_disp_panel->max_bpp;
+ if (bpp == 12)
+ bpp = 16;
+ ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
+ (unsigned int)panel->height, bpp,
+ cfg->raster_order);
+ if (ret < 0)
+ return ret;
+
+ /* Configure FDD */
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
+ (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
+
+ return 0;
+}
+
+static void lcdc_dma_start(void)
+{
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(0,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(0,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+}
+
+static u32 lcdc_irq_handler(void)
+{
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
+ u32 reg_ras;
+
+ if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ debug("LCD_SYNC_LOST\n");
+ lcd_disable_raster();
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+ lcd_enable_raster();
+ return LCD_SYNC_LOST;
+ } else if (stat & LCD_PL_LOAD_DONE) {
+ debug("LCD_PL_LOAD_DONE\n");
+ /*
+ * Must disable raster before changing state of any control bit.
+ * And also must be disabled before clearing the PL loading
+ * interrupt via the following write to the status register. If
+ * this is done after then one gets multiple PL done interrupts.
+ */
+ lcd_disable_raster();
+
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+ /* Disable PL completion inerrupt */
+ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ reg_ras &= ~LCD_PL_ENABLE;
+ lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+ /* Setup and start data loading mode */
+ lcd_blit(LOAD_DATA, par);
+ return LCD_PL_LOAD_DONE;
+ } else {
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+ if (stat & LCD_END_OF_FRAME0)
+ debug("LCD_END_OF_FRAME0\n");
+
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ par->vsync_flag = 1;
+ return LCD_END_OF_FRAME0;
+ }
+ return stat;
+}
+
+static u32 wait_for_event(u32 event)
+{
+ u32 timeout = 50000;
+ u32 ret;
+
+ do {
+ ret = lcdc_irq_handler();
+ udelay(1000);
+ } while (!(ret & event));
+
+ if (timeout <= 0) {
+ printf("%s: event %d not hit\n", __func__, event);
+ return -1;
+ }
+
+ return 0;
+
+}
+
+void *video_hw_init(void)
+{
+ struct da8xx_fb_par *par;
+ int ret;
+ u32 size;
+ char *p;
+
+ if (!lcd_panel) {
+ printf("Display not initialized\n");
+ return NULL;
+ }
+ gpanel.winSizeX = lcd_panel->width;
+ gpanel.winSizeY = lcd_panel->height;
+ gpanel.plnSizeX = lcd_panel->width;
+ gpanel.plnSizeY = lcd_panel->height;
+
+ switch (bits_x_pixel) {
+ case 24:
+ gpanel.gdfBytesPP = 4;
+ gpanel.gdfIndex = GDF_32BIT_X888RGB;
+ break;
+ case 16:
+ gpanel.gdfBytesPP = 2;
+ gpanel.gdfIndex = GDF_16BIT_565RGB;
+ break;
+ default:
+ gpanel.gdfBytesPP = 1;
+ gpanel.gdfIndex = GDF__8BIT_INDEX;
+ break;
+ }
+
+ da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
+
+ debug("Resolution: %dx%d %x\n",
+ gpanel.winSizeX,
+ gpanel.winSizeY,
+ lcd_cfg.bpp);
+
+ size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
+ da8xx_fb_info = malloc(size);
+ debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
+
+ if (!da8xx_fb_info) {
+ printf("Memory allocation failed for fb_info\n");
+ return NULL;
+ }
+ memset(da8xx_fb_info, 0, size);
+ p = (char *)da8xx_fb_info;
+ da8xx_fb_info->par = p + sizeof(struct fb_info);
+ debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
+
+ par = da8xx_fb_info->par;
+ par->pxl_clk = lcd_panel->pxl_clk;
+
+ if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
+ printf("lcd_init failed\n");
+ ret = -EFAULT;
+ goto err_release_fb;
+ }
+
+ /* allocate frame buffer */
+ par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
+ par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
+
+ par->vram_virt = malloc(par->vram_size);
+
+ par->vram_phys = (dma_addr_t) par->vram_virt;
+ debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
+ (unsigned int)par->vram_size,
+ (unsigned int)par->vram_virt);
+ if (!par->vram_virt) {
+ printf("GLCD: malloc for frame buffer failed\n");
+ ret = -EINVAL;
+ goto err_release_fb;
+ }
+
+ gpanel.frameAdrs = (unsigned int)par->vram_virt;
+ da8xx_fb_info->screen_base = (char *) par->vram_virt;
+ da8xx_fb_fix.smem_start = gpanel.frameAdrs;
+ da8xx_fb_fix.smem_len = par->vram_size;
+ da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
+
+ par->dma_start = par->vram_phys;
+ par->dma_end = par->dma_start + lcd_panel->height *
+ da8xx_fb_fix.line_length - 1;
+
+ /* allocate palette buffer */
+ par->v_palette_base = malloc(PALETTE_SIZE);
+ if (!par->v_palette_base) {
+ printf("GLCD: malloc for palette buffer failed\n");
+ goto err_release_fb_mem;
+ }
+ memset(par->v_palette_base, 0, PALETTE_SIZE);
+ par->p_palette_base = (unsigned int)par->v_palette_base;
+
+ /* Initialize par */
+ da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
+
+ da8xx_fb_var.xres = lcd_panel->width;
+ da8xx_fb_var.xres_virtual = lcd_panel->width;
+
+ da8xx_fb_var.yres = lcd_panel->height;
+ da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
+
+ da8xx_fb_var.grayscale =
+ lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+ da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
+
+ da8xx_fb_var.hsync_len = lcd_panel->hsw;
+ da8xx_fb_var.vsync_len = lcd_panel->vsw;
+
+ /* Initialize fbinfo */
+ da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+ da8xx_fb_info->fix = da8xx_fb_fix;
+ da8xx_fb_info->var = da8xx_fb_var;
+ da8xx_fb_info->pseudo_palette = par->pseudo_palette;
+ da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
+ FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+
+ /* Clear interrupt */
+ memset((void *)par->vram_virt, 0, par->vram_size);
+ lcd_disable_raster();
+ lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+ debug("Palette at 0x%x size %d\n", par->p_palette_base,
+ par->palette_sz);
+ lcdc_dma_start();
+
+ /* Load a default palette */
+ fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
+
+ /* Check that the palette is loaded */
+ wait_for_event(LCD_PL_LOAD_DONE);
+
+ /* Wait until DMA is working */
+ wait_for_event(LCD_END_OF_FRAME0);
+
+ return (void *)&gpanel;
+
+err_release_fb_mem:
+ free(par->vram_virt);
+
+err_release_fb:
+ free(da8xx_fb_info);
+
+ return NULL;
+}
+
+void video_set_lut(unsigned int index, /* color number */
+ unsigned char r, /* red */
+ unsigned char g, /* green */
+ unsigned char b /* blue */
+ )
+{
+
+ return;
+}
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
+{
+ lcd_panel = panel;
+ bits_x_pixel = bits_pixel;
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-05 9:43 ` [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx Stefano Babic
@ 2011-10-06 22:14 ` Anatolij Gustschin
2011-10-06 22:22 ` stefano babic
2011-10-06 22:32 ` Wolfgang Denk
1 sibling, 1 reply; 28+ messages in thread
From: Anatolij Gustschin @ 2011-10-06 22:14 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Wed, 5 Oct 2011 11:43:36 +0200
Stefano Babic <sbabic@denx.de> wrote:
> The patch is a port of the Linux driver da8xx-fb.c used
> on davinci da8xx and OMAP-L138 boards.
>
> Last commit seen on this driver used as base
> for porting is 1db41e032d563eb47deab40dc5595be306b143ba
> (video: da8xx-fb: fix section mismatch warning)
>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> CC: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Anatolij Gustschin <agust@denx.de>
> ---
> arch/arm/include/asm/arch-davinci/da8xx-fb.h | 122 ++++
> drivers/video/Makefile | 1 +
> drivers/video/da8xx-fb.c | 846 ++++++++++++++++++++++++++
> 3 files changed, 969 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-davinci/da8xx-fb.h
> create mode 100644 drivers/video/da8xx-fb.c
>
> diff --git a/arch/arm/include/asm/arch-davinci/da8xx-fb.h b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
> new file mode 100644
> index 0000000..88613a5
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
> @@ -0,0 +1,122 @@
> +/*
> + * Header file for TI DA8XX LCD controller platform data.
> + *
> + * Copyright (C) 2008-2009 MontaVista Software Inc.
> + * Copyright (C) 2008-2009 Texas Instruments Inc
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
Hmm, the whole driver is under GPL v2 or any later version, but this
header under GPL v2 only? Actually this doesn't make sense. Newly added
code should use GPLv3-compatible licensing, e.g. GPL v2 or any later version.
...
> +#if 0
> +/* ioctls */
> +#define FBIOGET_CONTRAST _IOR('F', 1, int)
> +#define FBIOPUT_CONTRAST _IOW('F', 2, int)
> +#define FBIGET_BRIGHTNESS _IOR('F', 3, int)
> +#define FBIPUT_BRIGHTNESS _IOW('F', 3, int)
> +#define FBIGET_COLOR _IOR('F', 5, int)
> +#define FBIPUT_COLOR _IOW('F', 6, int)
> +#define FBIPUT_HSYNC _IOW('F', 9, int)
> +#define FBIPUT_VSYNC _IOW('F', 10, int)
> +#endif
Please do not add dead code.
Thanks,
Anatolij
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-06 22:14 ` Anatolij Gustschin
@ 2011-10-06 22:22 ` stefano babic
0 siblings, 0 replies; 28+ messages in thread
From: stefano babic @ 2011-10-06 22:22 UTC (permalink / raw)
To: u-boot
Am 07/10/2011 00:14, schrieb Anatolij Gustschin:
> Hi Stefano,
>
Hi Anatolij,
>> +++ b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
>> @@ -0,0 +1,122 @@
>> +/*
>> + * Header file for TI DA8XX LCD controller platform data.
>> + *
>> + * Copyright (C) 2008-2009 MontaVista Software Inc.
>> + * Copyright (C) 2008-2009 Texas Instruments Inc
>> + *
>> + * This file is licensed under the terms of the GNU General Public License
>> + * version 2. This program is licensed "as is" without any warranty of any
>> + * kind, whether express or implied.
>> + */
>
> Hmm, the whole driver is under GPL v2 or any later version, but this
> header under GPL v2 only? Actually this doesn't make sense. Newly added
> code should use GPLv3-compatible licensing, e.g. GPL v2 or any later version.
Right - I will correct the whole header.
>
> ...
>> +#if 0
>> +/* ioctls */
>> +#define FBIOGET_CONTRAST _IOR('F', 1, int)
>> +#define FBIOPUT_CONTRAST _IOW('F', 2, int)
>> +#define FBIGET_BRIGHTNESS _IOR('F', 3, int)
>> +#define FBIPUT_BRIGHTNESS _IOW('F', 3, int)
>> +#define FBIGET_COLOR _IOR('F', 5, int)
>> +#define FBIPUT_COLOR _IOW('F', 6, int)
>> +#define FBIPUT_HSYNC _IOW('F', 9, int)
>> +#define FBIPUT_VSYNC _IOW('F', 10, int)
>> +#endif
>
> Please do not add dead code.
Thanks, I forget to drop it - fixed in V2.
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-05 9:43 ` [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx Stefano Babic
2011-10-06 22:14 ` Anatolij Gustschin
@ 2011-10-06 22:32 ` Wolfgang Denk
2011-10-06 22:44 ` stefano babic
1 sibling, 1 reply; 28+ messages in thread
From: Wolfgang Denk @ 2011-10-06 22:32 UTC (permalink / raw)
To: u-boot
Dear Stefano Babic,
In message <1317807819-17056-9-git-send-email-sbabic@denx.de> you wrote:
> The patch is a port of the Linux driver da8xx-fb.c used
> on davinci da8xx and OMAP-L138 boards.
Port? From where?
> Last commit seen on this driver used as base
> for porting is 1db41e032d563eb47deab40dc5595be306b143ba
> (video: da8xx-fb: fix section mismatch warning)
Which repository is this commit ID from? I cannot find it in the
U-Boot tree...
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I had the rare misfortune of being one of the first people to try and
implement a PL/1 compiler. -- T. Cheatham
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-06 22:32 ` Wolfgang Denk
@ 2011-10-06 22:44 ` stefano babic
2011-10-07 4:42 ` Wolfgang Denk
0 siblings, 1 reply; 28+ messages in thread
From: stefano babic @ 2011-10-06 22:44 UTC (permalink / raw)
To: u-boot
Am 07/10/2011 00:32, schrieb Wolfgang Denk:
> Dear Stefano Babic,
>
> In message <1317807819-17056-9-git-send-email-sbabic@denx.de> you wrote:
>> The patch is a port of the Linux driver da8xx-fb.c used
>> on davinci da8xx and OMAP-L138 boards.
>
> Port? From where?
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-06 22:44 ` stefano babic
@ 2011-10-07 4:42 ` Wolfgang Denk
0 siblings, 0 replies; 28+ messages in thread
From: Wolfgang Denk @ 2011-10-07 4:42 UTC (permalink / raw)
To: u-boot
Dear stefano babic,
In message <4E8E2F60.2050602@denx.de> you wrote:
>
> > In message <1317807819-17056-9-git-send-email-sbabic@denx.de> you wrote:
> >> The patch is a port of the Linux driver da8xx-fb.c used
> >> on davinci da8xx and OMAP-L138 boards.
> >
> > Port? From where?
>
> From the Linux Kernel, of course ;-)
Please say so in the commit message.
> > Which repository is this commit ID from? I cannot find it in the
> > U-Boot tree...
>
> This is the commit-id in the kernel tree. It states the last changes on
> this driver that I took as base for porting to U-Boot.
Ditto.
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There are two ways to write error-free programs. Only the third one
works.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 10/12] Davinci: ea20: added video support
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (7 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 09/12] VIDEO: davinci: add framebuffer to da8xx Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-06 21:12 ` Anatolij Gustschin
2011-10-05 9:43 ` [U-Boot] [PATCH 11/12] Davinci: ea20: added I2C support Stefano Babic
` (3 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
board/davinci/ea20/ea20.c | 62 +++++++++++++++++++++++++++++++++++++++++++++
include/configs/ea20.h | 14 +++++++++-
2 files changed, 75 insertions(+), 1 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index c28d8df..d581cdd 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -36,11 +36,27 @@
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/da8xx-fb.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+static const struct da8xx_panel lcd_panel = {
+ /* Casio COM57H531x */
+ .name = "Casio_COM57H531x",
+ .width = 640,
+ .height = 480,
+ .hfp = 12,
+ .hbp = 144,
+ .hsw = 30,
+ .vfp = 10,
+ .vbp = 35,
+ .vsw = 3,
+ .pxl_clk = 25000000,
+ .invert_pxl_clk = 0,
+};
+
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
@@ -100,6 +116,29 @@ const struct pinmux_config gpio_pins[] = {
{ pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/
};
+const struct pinmux_config lcd_pins[] = {
+ { pinmux(17), 2, 1 }, /* LCD_D_0 */
+ { pinmux(17), 2, 0 }, /* LCD_D_1 */
+ { pinmux(16), 2, 7 }, /* LCD_D_2 */
+ { pinmux(16), 2, 6 }, /* LCD_D_3 */
+ { pinmux(16), 2, 5 }, /* LCD_D_4 */
+ { pinmux(16), 2, 4 }, /* LCD_D_5 */
+ { pinmux(16), 2, 3 }, /* LCD_D_6 */
+ { pinmux(16), 2, 2 }, /* LCD_D_7 */
+ { pinmux(18), 2, 1 }, /* LCD_D_8 */
+ { pinmux(18), 2, 0 }, /* LCD_D_9 */
+ { pinmux(17), 2, 7 }, /* LCD_D_10 */
+ { pinmux(17), 2, 6 }, /* LCD_D_11 */
+ { pinmux(17), 2, 5 }, /* LCD_D_12 */
+ { pinmux(17), 2, 4 }, /* LCD_D_13 */
+ { pinmux(17), 2, 3 }, /* LCD_D_14 */
+ { pinmux(17), 2, 2 }, /* LCD_D_15 */
+ { pinmux(18), 2, 6 }, /* LCD_PCLK */
+ { pinmux(19), 2, 0 }, /* LCD_HSYNC */
+ { pinmux(19), 2, 1 }, /* LCD_VSYNC */
+ { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
+};
+
const struct pinmux_config halten_pin[] = {
{ pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */
};
@@ -112,6 +151,9 @@ static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(nand_pins),
#endif
+#ifdef CONFIG_VIDEO
+ PINMUX_ITEM(lcd_pins),
+#endif
};
static const struct lpsc_resource lpsc[] = {
@@ -120,6 +162,7 @@ static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART0 }, /* console */
{ DAVINCI_LPSC_GPIO },
+ { DAVINCI_LPSC_LCDC }, /* LCD */
};
int board_early_init_f(void)
@@ -208,6 +251,21 @@ int board_early_init_f(void)
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart0_ctrl_regs->pwremu_mgmt);
+ /*
+ * Reconfigure the LCDC priority to the highest to ensure that
+ * the throughput/latency requirements for the LCDC are met.
+ */
+ writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
+ &davinci_syscfg_regs->mstpri[2]);
+
+ /* Set LCD_B_PWR low to power up LCD Backlight*/
+ writel((readl(&gpio6_base->set_data) | (1 << 6)),
+ &gpio6_base->set_data);
+
+ /* Set DISP_ON low to disable LCD output*/
+ writel((readl(&gpio6_base->set_data) | (1 << 1)),
+ &gpio6_base->set_data);
+
return 0;
}
@@ -219,6 +277,8 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+ da8xx_video_init(&lcd_panel, 16);
+
return 0;
}
@@ -238,6 +298,8 @@ int board_late_init(void)
&gpio8_base->set_data);
writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir);
+ setenv("stdout", "serial");
+
return 0;
}
#endif /* BOARD_LATE_INIT */
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 7c9e4da..aeeed09 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -32,6 +32,7 @@
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOARD_EARLY_INIT_F
#define BOARD_LATE_INIT
+#define CONFIG_VIDEO
/*
* SoC Configuration
@@ -50,7 +51,7 @@
/*
* Memory Info
*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
@@ -109,6 +110,17 @@
#define CONFIG_SYS_NO_FLASH
#endif
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#endif
+
/*
* U-Boot general configuration
*/
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 10/12] Davinci: ea20: added video support
2011-10-05 9:43 ` [U-Boot] [PATCH 10/12] Davinci: ea20: added video support Stefano Babic
@ 2011-10-06 21:12 ` Anatolij Gustschin
0 siblings, 0 replies; 28+ messages in thread
From: Anatolij Gustschin @ 2011-10-06 21:12 UTC (permalink / raw)
To: u-boot
Hi Stefano, Sandeep,
On Wed, 5 Oct 2011 11:43:37 +0200
Stefano Babic <sbabic@denx.de> wrote:
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> Cc: Anatolij Gustschin <agust@denx.de>
> CC: Sandeep Paulraj <s-paulraj@ti.com>
> ---
> board/davinci/ea20/ea20.c | 62 +++++++++++++++++++++++++++++++++++++++++++++
> include/configs/ea20.h | 14 +++++++++-
> 2 files changed, 75 insertions(+), 1 deletions(-)
Acked-by: Anatolij Gustschin <agust@denx.de>
Anatolij
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 11/12] Davinci: ea20: added I2C support
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (8 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 10/12] Davinci: ea20: added video support Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 9:43 ` [U-Boot] [PATCH 12/12] Davinci: ea20: added PREBOOT to configuration Stefano Babic
` (2 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
board/davinci/ea20/ea20.c | 7 +++++++
include/configs/ea20.h | 8 ++++++++
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index d581cdd..720a360 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -65,6 +65,12 @@ static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 5 }
};
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+ { pinmux(4), 2, 2 },
+ { pinmux(4), 2, 3 }
+};
+
/* UART0 pin muxer settings */
static const struct pinmux_config uart_pins[] = {
{ pinmux(3), 2, 7 },
@@ -148,6 +154,7 @@ static const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(spi1_pins),
#endif
PINMUX_ITEM(uart_pins),
+ PINMUX_ITEM(i2c_pins),
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(nand_pins),
#endif
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index aeeed09..ceb84a4 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -87,6 +87,13 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/*
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
@@ -160,6 +167,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_I2C
#ifndef CONFIG_DRIVER_TI_EMAC
#undef CONFIG_CMD_NET
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 12/12] Davinci: ea20: added PREBOOT to configuration
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (9 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 11/12] Davinci: ea20: added I2C support Stefano Babic
@ 2011-10-05 9:43 ` Stefano Babic
2011-10-05 13:08 ` [U-Boot] [PATCH 13/13] Davinci: ea20: use gpio framework to access gpios Stefano Babic
2011-10-08 9:27 ` [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx Stefano Babic
12 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 9:43 UTC (permalink / raw)
To: u-boot
PREBOOT is used on the ea20 to load a splash image
at the start up.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
include/configs/ea20.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index ceb84a4..9b4b415 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -33,6 +33,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define BOARD_LATE_INIT
#define CONFIG_VIDEO
+#define CONFIG_PREBOOT
/*
* SoC Configuration
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 13/13] Davinci: ea20: use gpio framework to access gpios
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (10 preceding siblings ...)
2011-10-05 9:43 ` [U-Boot] [PATCH 12/12] Davinci: ea20: added PREBOOT to configuration Stefano Babic
@ 2011-10-05 13:08 ` Stefano Babic
2011-10-05 13:14 ` Laurence Withers
2011-10-08 9:27 ` [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx Stefano Babic
12 siblings, 1 reply; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 13:08 UTC (permalink / raw)
To: u-boot
Drop direct access to SOC's registers and use
the function of the GPIO driver for da8xx.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
CC: dzu at denx.de
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
This is added to an existing patchset
board/davinci/ea20/ea20.c | 32 +++++++++-----------------------
include/configs/ea20.h | 2 ++
2 files changed, 11 insertions(+), 23 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 720a360..e16c31b 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -35,7 +35,7 @@
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include <asm/arch/da8xx-fb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -182,29 +182,19 @@ int board_early_init_f(void)
return 1;
/* Set the RESETOUTn low */
- writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
+ gpio_direction_output(111, 0);
/* Set U0_SW0 low for UART0 as console*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
+ gpio_direction_output(106, 0);
/* Set U0_SW1 low for UART0 as console*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
+ gpio_direction_output(108, 0);
/* Set LCD_B_PWR low to power down LCD Backlight*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 6)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir);
+ gpio_direction_output(102, 0);
/* Set DISP_ON low to disable LCD output*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 1)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir);
+ gpio_direction_output(97, 0);
#ifndef CONFIG_USE_IRQ
irq_init();
@@ -266,12 +256,10 @@ int board_early_init_f(void)
&davinci_syscfg_regs->mstpri[2]);
/* Set LCD_B_PWR low to power up LCD Backlight*/
- writel((readl(&gpio6_base->set_data) | (1 << 6)),
- &gpio6_base->set_data);
+ gpio_set_value(102, 1);
/* Set DISP_ON low to disable LCD output*/
- writel((readl(&gpio6_base->set_data) | (1 << 1)),
- &gpio6_base->set_data);
+ gpio_set_value(97, 1);
return 0;
}
@@ -301,9 +289,7 @@ int board_late_init(void)
return 1;
/* Set HALTEN to high */
- writel((readl(&gpio8_base->set_data) | (1 << 6)),
- &gpio8_base->set_data);
- writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir);
+ gpio_direction_output(134, 1);
setenv("stdout", "serial");
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index b99c620..d01b605 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -48,6 +48,7 @@
#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
+#define CONFIG_DA8XX_GPIO
/*
* Memory Info
@@ -169,6 +170,7 @@
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_GPIO
#ifndef CONFIG_DRIVER_TI_EMAC
#undef CONFIG_CMD_NET
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 13/13] Davinci: ea20: use gpio framework to access gpios
2011-10-05 13:08 ` [U-Boot] [PATCH 13/13] Davinci: ea20: use gpio framework to access gpios Stefano Babic
@ 2011-10-05 13:14 ` Laurence Withers
2011-10-05 13:49 ` Stefano Babic
0 siblings, 1 reply; 28+ messages in thread
From: Laurence Withers @ 2011-10-05 13:14 UTC (permalink / raw)
To: u-boot
On Wed, Oct 05, 2011 at 03:08:24PM +0200, Stefano Babic wrote:
> Drop direct access to SOC's registers and use
> the function of the GPIO driver for da8xx.
Dear Stefano,
The da8xx GPIO driver also configures the pinmux for you.
Bye for now,
--
Laurence Withers, <lwithers@guralp.com> http://www.guralp.com/
Direct tel:+447753988197 or tel:+443333408643 Software Engineer
General support queries: <support@guralp.com> CMG-DCM CMG-EAM CMG-NAM
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 13/13] Davinci: ea20: use gpio framework to access gpios
2011-10-05 13:14 ` Laurence Withers
@ 2011-10-05 13:49 ` Stefano Babic
0 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-05 13:49 UTC (permalink / raw)
To: u-boot
On 10/05/2011 03:14 PM, Laurence Withers wrote:
> On Wed, Oct 05, 2011 at 03:08:24PM +0200, Stefano Babic wrote:
>> Drop direct access to SOC's registers and use
>> the function of the GPIO driver for da8xx.
>
> Dear Stefano,
>
> The da8xx GPIO driver also configures the pinmux for you.
>
> Bye for now,
That's true, but this was wanted. IMHO is the usage of the functions
gpio_request() and gpio_free() optional.
I decided to program myself the pinmux also for the gpio together with
the setup of the pinmux for the other controllers of the SOC, everything
in the ea20.c file.
this allows to see all code managing the pinmux on this board in one place.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-05 9:43 [U-Boot] [PATCH 01/12] Davinci: ea20: set console on UART0 Stefano Babic
` (11 preceding siblings ...)
2011-10-05 13:08 ` [U-Boot] [PATCH 13/13] Davinci: ea20: use gpio framework to access gpios Stefano Babic
@ 2011-10-08 9:27 ` Stefano Babic
2011-10-11 16:10 ` Anatolij Gustschin
12 siblings, 1 reply; 28+ messages in thread
From: Stefano Babic @ 2011-10-08 9:27 UTC (permalink / raw)
To: u-boot
The patch is a port from the framebuffer driver
of the Linux driver drivers/video/da8xx-fb.c, used
on davinci da8xx and OMAP-L138 boards.
As base for the port, the following commit (last changes
for this driver at the moment in the Linux kernel tree)
was taken:
commit 1db41e032d563eb47deab40dc5595be306b143ba
Author: axel lin <axel.lin@gmail.com>
Date: Tue Feb 22 01:52:42 2011 +0000
video: da8xx-fb: fix section mismatch warning
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
---
Changes:
- set a correct license header and drop dead code in da8xx-fb.h
(Anatolij Gustschin)
- change commit message adding better references to driver in linux
used for porting (Wolfgang Denk)
arch/arm/include/asm/arch-davinci/da8xx-fb.h | 126 ++++
drivers/video/Makefile | 1 +
drivers/video/da8xx-fb.c | 846 ++++++++++++++++++++++++++
3 files changed, 973 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-davinci/da8xx-fb.h
create mode 100644 drivers/video/da8xx-fb.c
diff --git a/arch/arm/include/asm/arch-davinci/da8xx-fb.h b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
new file mode 100644
index 0000000..6d2327c
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
@@ -0,0 +1,126 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef DA8XX_FB_H
+#define DA8XX_FB_H
+
+enum panel_type {
+ QVGA = 0
+};
+
+enum panel_shade {
+ MONOCHROME = 0,
+ COLOR_ACTIVE,
+ COLOR_PASSIVE,
+};
+
+enum raster_load_mode {
+ LOAD_DATA = 1,
+ LOAD_PALETTE,
+};
+
+struct display_panel {
+ enum panel_type panel_type; /* QVGA */
+ int max_bpp;
+ int min_bpp;
+ enum panel_shade panel_shade;
+};
+
+struct da8xx_panel {
+ const char name[25]; /* Full name <vendor>_<model> */
+ unsigned short width;
+ unsigned short height;
+ int hfp; /* Horizontal front porch */
+ int hbp; /* Horizontal back porch */
+ int hsw; /* Horizontal Sync Pulse Width */
+ int vfp; /* Vertical front porch */
+ int vbp; /* Vertical back porch */
+ int vsw; /* Vertical Sync Pulse Width */
+ unsigned int pxl_clk; /* Pixel clock */
+ unsigned char invert_pxl_clk; /* Invert Pixel clock */
+};
+
+struct da8xx_lcdc_platform_data {
+ const char manu_name[10];
+ void *controller_data;
+ const char type[25];
+ void (*panel_power_ctrl)(int);
+};
+
+struct lcd_ctrl_config {
+ const struct display_panel *p_disp_panel;
+
+ /* AC Bias Pin Frequency */
+ int ac_bias;
+
+ /* AC Bias Pin Transitions per Interrupt */
+ int ac_bias_intrpt;
+
+ /* DMA burst size */
+ int dma_burst_sz;
+
+ /* Bits per pixel */
+ int bpp;
+
+ /* FIFO DMA Request Delay */
+ int fdd;
+
+ /* TFT Alternative Signal Mapping (Only for active) */
+ unsigned char tft_alt_mode;
+
+ /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
+ unsigned char stn_565_mode;
+
+ /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+ unsigned char mono_8bit_mode;
+
+ /* Invert line clock */
+ unsigned char invert_line_clock;
+
+ /* Invert frame clock */
+ unsigned char invert_frm_clock;
+
+ /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+ unsigned char sync_edge;
+
+ /* Horizontal and Vertical Sync: Control: 0=ignore */
+ unsigned char sync_ctrl;
+
+ /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+ unsigned char raster_order;
+};
+
+struct lcd_sync_arg {
+ int back_porch;
+ int front_porch;
+ int pulse_width;
+};
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+
+#endif /* ifndef DA8XX_FB_H */
+
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 3790f91..7aafd8c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
+COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
new file mode 100644
index 0000000..bca9fb5
--- /dev/null
+++ b/drivers/video/da8xx-fb.c
@@ -0,0 +1,846 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include "videomodes.h"
+#include <asm/arch/da8xx-fb.h>
+
+#define DRIVER_NAME "da8xx_lcdc"
+
+/* LCD Status Register */
+#define LCD_END_OF_FRAME1 (1 << 9)
+#define LCD_END_OF_FRAME0 (1 << 8)
+#define LCD_PL_LOAD_DONE (1 << 6)
+#define LCD_FIFO_UNDERFLOW (1 << 5)
+#define LCD_SYNC_LOST (1 << 2)
+
+/* LCD DMA Control Register */
+#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
+#define LCD_DMA_BURST_1 0x0
+#define LCD_DMA_BURST_2 0x1
+#define LCD_DMA_BURST_4 0x2
+#define LCD_DMA_BURST_8 0x3
+#define LCD_DMA_BURST_16 0x4
+#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
+
+/* LCD Control Register */
+#define LCD_CLK_DIVISOR(x) ((x) << 8)
+#define LCD_RASTER_MODE 0x01
+
+/* LCD Raster Control Register */
+#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
+#define PALETTE_AND_DATA 0x00
+#define PALETTE_ONLY 0x01
+#define DATA_ONLY 0x02
+
+#define LCD_MONO_8BIT_MODE (1 << 9)
+#define LCD_RASTER_ORDER (1 << 8)
+#define LCD_TFT_MODE (1 << 7)
+#define LCD_UNDERFLOW_INT_ENA (1 << 6)
+#define LCD_PL_ENABLE (1 << 4)
+#define LCD_MONOCHROME_MODE (1 << 1)
+#define LCD_RASTER_ENABLE (1 << 0)
+#define LCD_TFT_ALT_ENABLE (1 << 23)
+#define LCD_STN_565_ENABLE (1 << 24)
+
+/* LCD Raster Timing 2 Register */
+#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
+#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
+#define LCD_SYNC_CTRL (1 << 25)
+#define LCD_SYNC_EDGE (1 << 24)
+#define LCD_INVERT_PIXEL_CLOCK (1 << 22)
+#define LCD_INVERT_LINE_CLOCK (1 << 21)
+#define LCD_INVERT_FRAME_CLOCK (1 << 20)
+
+/* LCD Block */
+struct da8xx_lcd_regs {
+ u32 revid;
+ u32 ctrl;
+ u32 stat;
+ u32 lidd_ctrl;
+ u32 lidd_cs0_conf;
+ u32 lidd_cs0_addr;
+ u32 lidd_cs0_data;
+ u32 lidd_cs1_conf;
+ u32 lidd_cs1_addr;
+ u32 lidd_cs1_data;
+ u32 raster_ctrl;
+ u32 raster_timing_0;
+ u32 raster_timing_1;
+ u32 raster_timing_2;
+ u32 raster_subpanel;
+ u32 reserved;
+ u32 dma_ctrl;
+ u32 dma_frm_buf_base_addr_0;
+ u32 dma_frm_buf_ceiling_addr_0;
+ u32 dma_frm_buf_base_addr_1;
+ u32 dma_frm_buf_ceiling_addr_1;
+};
+
+#define LCD_NUM_BUFFERS 1
+
+#define WSI_TIMEOUT 50
+#define PALETTE_SIZE 256
+#define LEFT_MARGIN 64
+#define RIGHT_MARGIN 64
+#define UPPER_MARGIN 32
+#define LOWER_MARGIN 32
+
+#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+static struct da8xx_lcd_regs *da8xx_fb_reg_base;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* graphics setup */
+static GraphicDevice gpanel;
+static const struct da8xx_panel *lcd_panel;
+static struct fb_info *da8xx_fb_info;
+static int bits_x_pixel;
+
+static inline unsigned int lcdc_read(u32 *addr)
+{
+ return (unsigned int)readl(addr);
+}
+
+static inline void lcdc_write(unsigned int val, u32 *addr)
+{
+ writel(val, addr);
+}
+
+struct da8xx_fb_par {
+ u32 p_palette_base;
+ unsigned char *v_palette_base;
+ dma_addr_t vram_phys;
+ unsigned long vram_size;
+ void *vram_virt;
+ unsigned int dma_start;
+ unsigned int dma_end;
+ struct clk *lcdc_clk;
+ int irq;
+ unsigned short pseudo_palette[16];
+ unsigned int palette_sz;
+ unsigned int pxl_clk;
+ int blank;
+ int vsync_flag;
+ int vsync_timeout;
+};
+
+
+/* Variable Screen Information */
+static struct fb_var_screeninfo da8xx_fb_var = {
+ .xoffset = 0,
+ .yoffset = 0,
+ .transp = {0, 0, 0},
+ .nonstd = 0,
+ .activate = 0,
+ .height = -1,
+ .width = -1,
+ .pixclock = 46666, /* 46us - AUO display */
+ .accel_flags = 0,
+ .left_margin = LEFT_MARGIN,
+ .right_margin = RIGHT_MARGIN,
+ .upper_margin = UPPER_MARGIN,
+ .lower_margin = LOWER_MARGIN,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_fix_screeninfo da8xx_fb_fix = {
+ .id = "DA8xx FB Drv",
+ .type = FB_TYPE_PACKED_PIXELS,
+ .type_aux = 0,
+ .visual = FB_VISUAL_PSEUDOCOLOR,
+ .xpanstep = 0,
+ .ypanstep = 1,
+ .ywrapstep = 0,
+ .accel = FB_ACCEL_NONE
+};
+
+static const struct display_panel disp_panel = {
+ QVGA,
+ 16,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 255,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+/* Enable the Raster Engine of the LCD Controller */
+static inline void lcd_enable_raster(void)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ if (!(reg & LCD_RASTER_ENABLE))
+ lcdc_write(reg | LCD_RASTER_ENABLE,
+ &da8xx_fb_reg_base->raster_ctrl);
+}
+
+/* Disable the Raster Engine of the LCD Controller */
+static inline void lcd_disable_raster(void)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ if (reg & LCD_RASTER_ENABLE)
+ lcdc_write(reg & ~LCD_RASTER_ENABLE,
+ &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+{
+ u32 start;
+ u32 end;
+ u32 reg_ras;
+ u32 reg_dma;
+
+ /* init reg to clear PLM (loading mode) fields */
+ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ reg_ras &= ~(3 << 20);
+
+ reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
+
+ if (load_mode == LOAD_DATA) {
+ start = par->dma_start;
+ end = par->dma_end;
+
+ reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
+ reg_dma |= LCD_END_OF_FRAME_INT_ENA;
+
+#if (LCD_NUM_BUFFERS == 2)
+ reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#else
+ reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#endif
+
+ } else if (load_mode == LOAD_PALETTE) {
+ start = par->p_palette_base;
+ end = start + par->palette_sz - 1;
+
+ reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+ reg_ras |= LCD_PL_ENABLE;
+
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ }
+
+ lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
+ lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+ /*
+ * The Raster enable bit must be set after all other control fields are
+ * set.
+ */
+ lcd_enable_raster();
+}
+
+/* Configure the Burst Size of DMA */
+static int lcd_cfg_dma(int burst_size)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
+ switch (burst_size) {
+ case 1:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+ break;
+ case 2:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+ break;
+ case 4:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+ break;
+ case 8:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+ break;
+ case 16:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+ break;
+ default:
+ return -EINVAL;
+ }
+ lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
+
+ return 0;
+}
+
+static void lcd_cfg_ac_bias(int period, int transitions_per_int)
+{
+ u32 reg;
+
+ /* Set the AC Bias Period and Number of Transisitons per Interrupt */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
+ reg |= LCD_AC_BIAS_FREQUENCY(period) |
+ LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+}
+
+static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+ int front_porch)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
+ reg |= ((back_porch & 0xff) << 24)
+ | ((front_porch & 0xff) << 16)
+ | ((pulse_width & 0x3f) << 10);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+}
+
+static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+ int front_porch)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
+ reg |= ((back_porch & 0xff) << 24)
+ | ((front_porch & 0xff) << 16)
+ | ((pulse_width & 0x3f) << 10);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+}
+
+static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
+ LCD_MONO_8BIT_MODE |
+ LCD_MONOCHROME_MODE);
+
+ switch (cfg->p_disp_panel->panel_shade) {
+ case MONOCHROME:
+ reg |= LCD_MONOCHROME_MODE;
+ if (cfg->mono_8bit_mode)
+ reg |= LCD_MONO_8BIT_MODE;
+ break;
+ case COLOR_ACTIVE:
+ reg |= LCD_TFT_MODE;
+ if (cfg->tft_alt_mode)
+ reg |= LCD_TFT_ALT_ENABLE;
+ break;
+
+ case COLOR_PASSIVE:
+ if (cfg->stn_565_mode)
+ reg |= LCD_STN_565_ENABLE;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ /* enable additional interrupts here */
+ reg |= LCD_UNDERFLOW_INT_ENA;
+
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
+
+ if (cfg->sync_ctrl)
+ reg |= LCD_SYNC_CTRL;
+ else
+ reg &= ~LCD_SYNC_CTRL;
+
+ if (cfg->sync_edge)
+ reg |= LCD_SYNC_EDGE;
+ else
+ reg &= ~LCD_SYNC_EDGE;
+
+ if (cfg->invert_line_clock)
+ reg |= LCD_INVERT_LINE_CLOCK;
+ else
+ reg &= ~LCD_INVERT_LINE_CLOCK;
+
+ if (cfg->invert_frm_clock)
+ reg |= LCD_INVERT_FRAME_CLOCK;
+ else
+ reg &= ~LCD_INVERT_FRAME_CLOCK;
+
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+
+ return 0;
+}
+
+static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
+ u32 bpp, u32 raster_order)
+{
+ u32 reg;
+
+ /* Set the Panel Width */
+ /* Pixels per line = (PPL + 1)*16 */
+ /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
+ width &= 0x3f0;
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
+ reg &= 0xfffffc00;
+ reg |= ((width >> 4) - 1) << 4;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+
+ /* Set the Panel Height */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
+ reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+
+ /* Set the Raster Order of the Frame Buffer */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
+ if (raster_order)
+ reg |= LCD_RASTER_ORDER;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+ switch (bpp) {
+ case 1:
+ case 2:
+ case 4:
+ case 16:
+ par->palette_sz = 16 * 2;
+ break;
+
+ case 8:
+ par->palette_sz = 256 * 2;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ struct da8xx_fb_par *par = info->par;
+ unsigned short *palette = (unsigned short *) par->v_palette_base;
+ u_short pal;
+ int update_hw = 0;
+
+ if (regno > 255)
+ return 1;
+
+ if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+ return 1;
+
+ if (info->var.bits_per_pixel == 8) {
+ red >>= 4;
+ green >>= 8;
+ blue >>= 12;
+
+ pal = (red & 0x0f00);
+ pal |= (green & 0x00f0);
+ pal |= (blue & 0x000f);
+
+ if (palette[regno] != pal) {
+ update_hw = 1;
+ palette[regno] = pal;
+ }
+ } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+ red >>= (16 - info->var.red.length);
+ red <<= info->var.red.offset;
+
+ green >>= (16 - info->var.green.length);
+ green <<= info->var.green.offset;
+
+ blue >>= (16 - info->var.blue.length);
+ blue <<= info->var.blue.offset;
+
+ par->pseudo_palette[regno] = red | green | blue;
+
+ if (palette[0] != 0x4000) {
+ update_hw = 1;
+ palette[0] = 0x4000;
+ }
+ }
+
+ /* Update the palette in the h/w as needed. */
+ if (update_hw)
+ lcd_blit(LOAD_PALETTE, par);
+
+ return 0;
+}
+
+static void lcd_reset(struct da8xx_fb_par *par)
+{
+ /* Disable the Raster if previously Enabled */
+ lcd_disable_raster();
+
+ /* DMA has to be disabled */
+ lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
+ lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
+{
+ unsigned int lcd_clk, div;
+
+ /* Get clock from sysclk2 */
+ lcd_clk = clk_get(2);
+
+ div = lcd_clk / par->pxl_clk;
+ debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
+ lcd_clk, div, par->pxl_clk);
+
+ /* Configure the LCD clock divisor. */
+ lcdc_write(LCD_CLK_DIVISOR(div) |
+ (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+}
+
+static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+ const struct da8xx_panel *panel)
+{
+ u32 bpp;
+ int ret = 0;
+
+ lcd_reset(par);
+
+ /* Calculate the divider */
+ lcd_calc_clk_divider(par);
+
+ if (panel->invert_pxl_clk)
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
+ LCD_INVERT_PIXEL_CLOCK),
+ &da8xx_fb_reg_base->raster_timing_2);
+ else
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
+ ~LCD_INVERT_PIXEL_CLOCK),
+ &da8xx_fb_reg_base->raster_timing_2);
+
+ /* Configure the DMA burst size. */
+ ret = lcd_cfg_dma(cfg->dma_burst_sz);
+ if (ret < 0)
+ return ret;
+
+ /* Configure the AC bias properties. */
+ lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
+
+ /* Configure the vertical and horizontal sync properties. */
+ lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
+ lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+
+ /* Configure for disply */
+ ret = lcd_cfg_display(cfg);
+ if (ret < 0)
+ return ret;
+
+ if (QVGA != cfg->p_disp_panel->panel_type)
+ return -EINVAL;
+
+ if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+ cfg->bpp >= cfg->p_disp_panel->min_bpp)
+ bpp = cfg->bpp;
+ else
+ bpp = cfg->p_disp_panel->max_bpp;
+ if (bpp == 12)
+ bpp = 16;
+ ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
+ (unsigned int)panel->height, bpp,
+ cfg->raster_order);
+ if (ret < 0)
+ return ret;
+
+ /* Configure FDD */
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
+ (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
+
+ return 0;
+}
+
+static void lcdc_dma_start(void)
+{
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(0,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(0,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+}
+
+static u32 lcdc_irq_handler(void)
+{
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
+ u32 reg_ras;
+
+ if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ debug("LCD_SYNC_LOST\n");
+ lcd_disable_raster();
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+ lcd_enable_raster();
+ return LCD_SYNC_LOST;
+ } else if (stat & LCD_PL_LOAD_DONE) {
+ debug("LCD_PL_LOAD_DONE\n");
+ /*
+ * Must disable raster before changing state of any control bit.
+ * And also must be disabled before clearing the PL loading
+ * interrupt via the following write to the status register. If
+ * this is done after then one gets multiple PL done interrupts.
+ */
+ lcd_disable_raster();
+
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+ /* Disable PL completion inerrupt */
+ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ reg_ras &= ~LCD_PL_ENABLE;
+ lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+ /* Setup and start data loading mode */
+ lcd_blit(LOAD_DATA, par);
+ return LCD_PL_LOAD_DONE;
+ } else {
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+ if (stat & LCD_END_OF_FRAME0)
+ debug("LCD_END_OF_FRAME0\n");
+
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ par->vsync_flag = 1;
+ return LCD_END_OF_FRAME0;
+ }
+ return stat;
+}
+
+static u32 wait_for_event(u32 event)
+{
+ u32 timeout = 50000;
+ u32 ret;
+
+ do {
+ ret = lcdc_irq_handler();
+ udelay(1000);
+ } while (!(ret & event));
+
+ if (timeout <= 0) {
+ printf("%s: event %d not hit\n", __func__, event);
+ return -1;
+ }
+
+ return 0;
+
+}
+
+void *video_hw_init(void)
+{
+ struct da8xx_fb_par *par;
+ int ret;
+ u32 size;
+ char *p;
+
+ if (!lcd_panel) {
+ printf("Display not initialized\n");
+ return NULL;
+ }
+ gpanel.winSizeX = lcd_panel->width;
+ gpanel.winSizeY = lcd_panel->height;
+ gpanel.plnSizeX = lcd_panel->width;
+ gpanel.plnSizeY = lcd_panel->height;
+
+ switch (bits_x_pixel) {
+ case 24:
+ gpanel.gdfBytesPP = 4;
+ gpanel.gdfIndex = GDF_32BIT_X888RGB;
+ break;
+ case 16:
+ gpanel.gdfBytesPP = 2;
+ gpanel.gdfIndex = GDF_16BIT_565RGB;
+ break;
+ default:
+ gpanel.gdfBytesPP = 1;
+ gpanel.gdfIndex = GDF__8BIT_INDEX;
+ break;
+ }
+
+ da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
+
+ debug("Resolution: %dx%d %x\n",
+ gpanel.winSizeX,
+ gpanel.winSizeY,
+ lcd_cfg.bpp);
+
+ size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
+ da8xx_fb_info = malloc(size);
+ debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
+
+ if (!da8xx_fb_info) {
+ printf("Memory allocation failed for fb_info\n");
+ return NULL;
+ }
+ memset(da8xx_fb_info, 0, size);
+ p = (char *)da8xx_fb_info;
+ da8xx_fb_info->par = p + sizeof(struct fb_info);
+ debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
+
+ par = da8xx_fb_info->par;
+ par->pxl_clk = lcd_panel->pxl_clk;
+
+ if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
+ printf("lcd_init failed\n");
+ ret = -EFAULT;
+ goto err_release_fb;
+ }
+
+ /* allocate frame buffer */
+ par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
+ par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
+
+ par->vram_virt = malloc(par->vram_size);
+
+ par->vram_phys = (dma_addr_t) par->vram_virt;
+ debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
+ (unsigned int)par->vram_size,
+ (unsigned int)par->vram_virt);
+ if (!par->vram_virt) {
+ printf("GLCD: malloc for frame buffer failed\n");
+ ret = -EINVAL;
+ goto err_release_fb;
+ }
+
+ gpanel.frameAdrs = (unsigned int)par->vram_virt;
+ da8xx_fb_info->screen_base = (char *) par->vram_virt;
+ da8xx_fb_fix.smem_start = gpanel.frameAdrs;
+ da8xx_fb_fix.smem_len = par->vram_size;
+ da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
+
+ par->dma_start = par->vram_phys;
+ par->dma_end = par->dma_start + lcd_panel->height *
+ da8xx_fb_fix.line_length - 1;
+
+ /* allocate palette buffer */
+ par->v_palette_base = malloc(PALETTE_SIZE);
+ if (!par->v_palette_base) {
+ printf("GLCD: malloc for palette buffer failed\n");
+ goto err_release_fb_mem;
+ }
+ memset(par->v_palette_base, 0, PALETTE_SIZE);
+ par->p_palette_base = (unsigned int)par->v_palette_base;
+
+ /* Initialize par */
+ da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
+
+ da8xx_fb_var.xres = lcd_panel->width;
+ da8xx_fb_var.xres_virtual = lcd_panel->width;
+
+ da8xx_fb_var.yres = lcd_panel->height;
+ da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
+
+ da8xx_fb_var.grayscale =
+ lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+ da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
+
+ da8xx_fb_var.hsync_len = lcd_panel->hsw;
+ da8xx_fb_var.vsync_len = lcd_panel->vsw;
+
+ /* Initialize fbinfo */
+ da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+ da8xx_fb_info->fix = da8xx_fb_fix;
+ da8xx_fb_info->var = da8xx_fb_var;
+ da8xx_fb_info->pseudo_palette = par->pseudo_palette;
+ da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
+ FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+
+ /* Clear interrupt */
+ memset((void *)par->vram_virt, 0, par->vram_size);
+ lcd_disable_raster();
+ lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+ debug("Palette at 0x%x size %d\n", par->p_palette_base,
+ par->palette_sz);
+ lcdc_dma_start();
+
+ /* Load a default palette */
+ fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
+
+ /* Check that the palette is loaded */
+ wait_for_event(LCD_PL_LOAD_DONE);
+
+ /* Wait until DMA is working */
+ wait_for_event(LCD_END_OF_FRAME0);
+
+ return (void *)&gpanel;
+
+err_release_fb_mem:
+ free(par->vram_virt);
+
+err_release_fb:
+ free(da8xx_fb_info);
+
+ return NULL;
+}
+
+void video_set_lut(unsigned int index, /* color number */
+ unsigned char r, /* red */
+ unsigned char g, /* green */
+ unsigned char b /* blue */
+ )
+{
+
+ return;
+}
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
+{
+ lcd_panel = panel;
+ bits_x_pixel = bits_pixel;
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-08 9:27 ` [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx Stefano Babic
@ 2011-10-11 16:10 ` Anatolij Gustschin
2011-10-12 8:42 ` Stefano Babic
0 siblings, 1 reply; 28+ messages in thread
From: Anatolij Gustschin @ 2011-10-11 16:10 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Sat, 8 Oct 2011 11:27:34 +0200
Stefano Babic <sbabic@denx.de> wrote:
> The patch is a port from the framebuffer driver
> of the Linux driver drivers/video/da8xx-fb.c, used
> on davinci da8xx and OMAP-L138 boards.
>
> As base for the port, the following commit (last changes
> for this driver at the moment in the Linux kernel tree)
> was taken:
>
> commit 1db41e032d563eb47deab40dc5595be306b143ba
> Author: axel lin <axel.lin@gmail.com>
> Date: Tue Feb 22 01:52:42 2011 +0000
>
> video: da8xx-fb: fix section mismatch warning
>
> Signed-off-by: Axel Lin <axel.lin@gmail.com>
> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> CC: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Anatolij Gustschin <agust@denx.de>
> ---
>
> Changes:
>
> - set a correct license header and drop dead code in da8xx-fb.h
> (Anatolij Gustschin)
> - change commit message adding better references to driver in linux
> used for porting (Wolfgang Denk)
Thanks for these fixes. When applying this patch I see:
$ git am /tmp/\[PATCH\ V2\ 09_12\]\ VIDEO\:\ davinci\:\ add\ framebuffer\ to\ da8xx
Applying: VIDEO: davinci: add framebuffer to da8xx
/home/ag/u-boot/u-boot-move-new-host/u-boot-video/.git/rebase-apply/patch:22: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
This is due to the trailing empty line in
"arch/arm/include/asm/arch-davinci/da8xx-fb.h" I'think.
Can you please fix it also?
Then a fixed patch can go via TI ARM tree together with other patches
in this series. For a fixed patch you can add my
Acked-by: Anatolij Gustschin <agust@denx.de>
Thanks,
Anatolij
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-11 16:10 ` Anatolij Gustschin
@ 2011-10-12 8:42 ` Stefano Babic
2011-10-12 9:06 ` Anatolij Gustschin
0 siblings, 1 reply; 28+ messages in thread
From: Stefano Babic @ 2011-10-12 8:42 UTC (permalink / raw)
To: u-boot
On 10/11/2011 06:10 PM, Anatolij Gustschin wrote:
> Hi Stefano,
Hi Anatolij,
>
> Thanks for these fixes. When applying this patch I see:
>
> $ git am /tmp/\[PATCH\ V2\ 09_12\]\ VIDEO\:\ davinci\:\ add\ framebuffer\ to\ da8xx
> Applying: VIDEO: davinci: add framebuffer to da8xx
> /home/ag/u-boot/u-boot-move-new-host/u-boot-video/.git/rebase-apply/patch:22: new blank line at EOF.
> +
> warning: 1 line adds whitespace errors.
>
> This is due to the trailing empty line in
> "arch/arm/include/asm/arch-davinci/da8xx-fb.h" I'think.
> Can you please fix it also?
I have tried, no luck. I wonder that in my case I get a different line
for error:
/home/stefano/Projects/imx/u-boot-imx/.git/rebase-apply/patch:14: new
blank line at EOF.
Removing the empty line and the newline after the GIT version at the end
of the file makes no change - I still get this error.
"new blank line" suggets me that it is something after the patch itself,
but I have no idea where I should check. The patch seems correct. With
"git am --whitespace=fix", the patch is applied, but there is no other
hints about this issue.
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-12 8:42 ` Stefano Babic
@ 2011-10-12 9:06 ` Anatolij Gustschin
2011-10-12 9:35 ` Stefano Babic
0 siblings, 1 reply; 28+ messages in thread
From: Anatolij Gustschin @ 2011-10-12 9:06 UTC (permalink / raw)
To: u-boot
On Wed, 12 Oct 2011 10:42:21 +0200
Stefano Babic <sbabic@denx.de> wrote:
> On 10/11/2011 06:10 PM, Anatolij Gustschin wrote:
> > Hi Stefano,
>
> Hi Anatolij,
Hi Stefano,
> > Thanks for these fixes. When applying this patch I see:
> >
> > $ git am /tmp/\[PATCH\ V2\ 09_12\]\ VIDEO\:\ davinci\:\ add\ framebuffer\ to\ da8xx
> > Applying: VIDEO: davinci: add framebuffer to da8xx
> > /home/ag/u-boot/u-boot-move-new-host/u-boot-video/.git/rebase-apply/patch:22: new blank line at EOF.
> > +
> > warning: 1 line adds whitespace errors.
> >
> > This is due to the trailing empty line in
> > "arch/arm/include/asm/arch-davinci/da8xx-fb.h" I'think.
> > Can you please fix it also?
>
> I have tried, no luck. I wonder that in my case I get a different line
> for error:
>
> /home/stefano/Projects/imx/u-boot-imx/.git/rebase-apply/patch:14: new
> blank line at EOF.
>
> Removing the empty line and the newline after the GIT version at the end
> of the file makes no change - I still get this error.
>
> "new blank line" suggets me that it is something after the patch itself,
> but I have no idea where I should check. The patch seems correct. With
> "git am --whitespace=fix", the patch is applied, but there is no other
> hints about this issue.
git am complains since there is a blank line at the end of the
added arch/arm/include/asm/arch-davinci/da8xx-fb.h file.
OK, there is no need to resubmit this patch since it can be applied
with "--whitespace=fix" option.
Thanks,
Anatolij
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/12] VIDEO: davinci: add framebuffer to da8xx
2011-10-12 9:06 ` Anatolij Gustschin
@ 2011-10-12 9:35 ` Stefano Babic
0 siblings, 0 replies; 28+ messages in thread
From: Stefano Babic @ 2011-10-12 9:35 UTC (permalink / raw)
To: u-boot
On 10/12/2011 11:06 AM, Anatolij Gustschin wrote:
> OK, there is no need to resubmit this patch since it can be applied
> with "--whitespace=fix" option.
Ok, thanks.
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 28+ messages in thread