[U-Boot] [PATCH 0/2]: OMAP3 SPL updates

[U-Boot] [PATCH 0/2]: OMAP3 SPL updates

[Tom Rini]

Hey all,

The following short series does two things.  First, it re-works where
we do memory initalization in SPL for OMAP3 to be board-specific.
This is needed since in many cases (beagleboard, omap3evm) what timings
we set depend on what hardware we detect ourself to be running on.  Second,
along those same lines what omap_rev_string tells us is doing to be
board specific as well so provide a weak version in the common omap SPL
code and lets it be replaced as needed.

-- 
Tom

[U-Boot] [PATCH 1/2] OMAP3 SPL: Rework memory initalization and devkit 8000 support

[Tom Rini]

This changes to making the board be responsible for providing a
memory initialization function for SPL and converts the existing
function to provide these services for devkit 8000.  As part of this
suffix the Micron DDR settings with their speed.

Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/omap3/sdrc.c             |   46 +++++++++------------------
 arch/arm/include/asm/arch-omap3/mem.h       |   42 +++++--------------------
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 board/timll/devkit8000/devkit8000.c         |   24 ++++++++++++++
 4 files changed, 48 insertions(+), 65 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 0dd1955..7f81eb9 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -111,13 +111,21 @@ u32 get_sdr_cs_offset(u32 cs)
 /*
  * do_sdrc_init -
  *  - Initialize the SDRAM for use.
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *    time depending on memory configuration from stack+global context
+ *  - Code called once in C-Stack only context for CS0 and with early being
+ *    true and a possible 2nd time depending on memory configuration from
+ *    stack+global context.
  */
 void do_sdrc_init(u32 cs, u32 early)
 {
-	struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
+	struct sdrc_actim *sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+	struct sdrc_actim *sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 
+	/*
+	 * When called in the early context this may be SPL and we will
+	 * need to set all of the timings.  This ends up being board
+	 * specific so we call a helper function to take care of this
+	 * for us.
+	 */
 	if (early) {
 		/* reset sdrc controller */
 		writel(SOFTRESET, &sdrc_base->sysconfig);
@@ -128,40 +136,18 @@ void do_sdrc_init(u32 cs, u32 early)
 		/* setup sdrc to ball mux */
 		writel(SDRC_SHARING, &sdrc_base->sharing);
 
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
+		/* Disable Power Down of CKE because of 1 CKE on combo part */
 		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
 				&sdrc_base->power);
 
 		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 		sdelay(0x20000);
-	}
 
-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
- * to prevent this to be build in non-SPL build */
 #ifdef CONFIG_SPL_BUILD
-	/* If we use a SPL there is no x-loader nor config header so we have
-	 * to do the job ourselfs
-	 */
-	if (cs == CS0) {
-		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-		/* General SDRC config */
-		writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
-		writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
-
-		/* AC timings */
-		writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
-		writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
-
-		/* Initialize */
-		writel(CMD_NOP, &sdrc_base->cs[cs].manual);
-		writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
-		writel(V_MR, &sdrc_base->cs[cs].mr);
-	}
+		/* setup timings */
+		board_early_sdrc_init(sdrc_base, sdrc_actim_base0);
 #endif
+	}
 
 	/*
 	 * SDRC timings are set up by x-load or config header
@@ -170,8 +156,6 @@ void do_sdrc_init(u32 cs, u32 early)
 	 * configure CS1 to handle this ommission
 	 */
 	if (cs == CS1) {
-		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-		sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 		writel(readl(&sdrc_base->cs[CS0].mcfg),
 			&sdrc_base->cs[CS1].mcfg);
 		writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 8e28f77..90ec573 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -138,15 +138,15 @@ enum {
 #define MICRON_CASWIDTH			0x5
 #define MICRON_RASWIDTH			0x2
 #define MICRON_LOCKSTATUS		0x0
-#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
-	(MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
-	(MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
-	(MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
-	(MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
+#define MICRON_V_MCFG_165 		((MICRON_LOCKSTATUS << 30) | \
+	(MICRON_RASWIDTH << 24) | (MICRON_CASWIDTH << 20) | \
+	(MICRON_ADDRMUXLEGACY << 19) | (MICRON_RAMSIZE << 8) | \
+	(MICRON_BANKALLOCATION << 6) | (MICRON_B32NOT16 << 4) | \
+	(MICRON_DEEPPD << 3) | (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
 
-#define MICRON_ARCV				2030
-#define MICRON_ARE				0x1
-#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
+#define MICRON_ARCV_165		0x4e2
+#define MICRON_ARE		0x1
+#define MICRON_V_RFR_CTRL_165	((MICRON_ARCV_165 << 8) | (MICRON_ARE))
 
 #define MICRON_BL				0x2
 #define MICRON_SIL				0x0
@@ -194,32 +194,6 @@ enum {
 		(NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
 		(NUMONYX_TWTR_165 << 16))
 
-#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
-#endif
-
-#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
-#define V_MCFG			MICRON_V_MCFG
-#define V_RFR_CTRL		MICRON_V_RFR_CTRL
-#define V_MR			MICRON_V_MR
-#endif
-
-#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
-#endif
-
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
-#error "Please choose the right DDR type in config header"
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
-#error "Please choose the right DDR type in config header"
-#endif
-
 /*
  * GPMC settings -
  * Definitions is as per the following format
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 7b60051..7f2631e 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -38,6 +38,7 @@ void per_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+void board_early_sdrc_init(struct sdrc *, struct sdrc_actim *);
 void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index f50d113..100cc59 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -138,3 +138,27 @@ int board_eth_init(bd_t *bis)
 	return dm9000_initialize(bis);
 }
 #endif
+
+/*
+ * Routine: board_early_sdrc_init
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings outself on the first bank.
+ */
+void board_early_sdrc_init(struct sdrc *sdrc_base, struct sdrc_actim *sdrc_actim_base0)
+{
+	/* General SDRC config */
+	writel(MICRON_V_MCFG_165, &sdrc_base->cs[CS0].mcfg);
+	writel(MICRON_V_RFR_CTRL_165, &sdrc_base->cs[CS0].rfr_ctrl);
+
+	/* AC timings */
+	writel(MICRON_V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+	writel(MICRON_V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+
+	/* Initialize */
+	writel(CMD_NOP, &sdrc_base->cs[CS0].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[CS0].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[CS0].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[CS0].manual);
+
+	writel(MICRON_V_MR, &sdrc_base->cs[CS0].mr);
+}
-- 
1.7.0.4

[U-Boot] [PATCH 2/2] OMAP3 SPL: Provide weak omap_rev_string

[Tom Rini]

We add an weak version of omap_rev_string in omap-common/spl.c
and while at it drop the omap3 version.  Move the prototype over
to <asm/omap_common.h> with the other SPL functions.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/omap-common/spl.c        |    8 ++++++++
 arch/arm/cpu/armv7/omap3/board.c            |    6 ------
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 -
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 -
 arch/arm/include/asm/omap_common.h          |    1 +
 5 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index c76fea6..4db7a7b 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -161,3 +161,11 @@ void preloader_console_init(void)
 	omap_rev_string(rev_string_buffer);
 	printf("Texas Instruments %s\n", rev_string_buffer);
 }
+
+void __omap_rev_string(char *str)
+{
+	sprintf(str, "Revision detection unimplemented");
+}
+
+void omap_rev_string(char *str)
+	__attribute__((weak, alias("__omap_rev_string")));
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 1b3ef69..a9fdb4f 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -450,9 +450,3 @@ void enable_caches(void)
 	dcache_enable();
 }
 #endif
-
-void omap_rev_string(char *omap_rev_string)
-{
-	sprintf(omap_rev_string, "OMAP3, sorry revision detection" \
-		" unimplemented");
-}
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 7f2631e..1fc1c12 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -72,5 +72,4 @@ void power_init_r(void);
 void dieid_num_r(void);
 void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
 void omap3_gp_romcode_call(u32 service_id, u32 parameter);
-void omap_rev_string(char *omap_rev_string);
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index a81f8e5..1aacbb1 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -43,7 +43,6 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
-void omap_rev_string(char *omap4_rev_string);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 66d6b71..3f2f004 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -77,6 +77,7 @@ u32 omap_boot_mode(void);
 
 /* SPL common function s*/
 void spl_parse_image_header(const struct image_header *header);
+void omap_rev_string(char *omap_rev_string);
 
 /* NAND SPL functions */
 void spl_nand_load_image(void);
-- 
1.7.0.4

[U-Boot] [PATCH 1/2] OMAP3 SPL: Rework memory initalization and devkit 8000 support

[Wolfgang Denk]

Dear Tom Rini,

In message <1317740363-7033-2-git-send-email-trini@ti.com> you wrote:
> This changes to making the board be responsible for providing a
> memory initialization function for SPL and converts the existing
> function to provide these services for devkit 8000.  As part of this
> suffix the Micron DDR settings with their speed.
> 
> Cc: Frederik Kriewitz <frederik@kriewitz.eu>
> Signed-off-by: Tom Rini <trini@ti.com>
> ---
>  arch/arm/cpu/armv7/omap3/sdrc.c             |   46 +++++++++------------------
>  arch/arm/include/asm/arch-omap3/mem.h       |   42 +++++--------------------
>  arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
>  board/timll/devkit8000/devkit8000.c         |   24 ++++++++++++++
>  4 files changed, 48 insertions(+), 65 deletions(-)

Checkpatch says:

total: 0 errors, 4 warnings, 165 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The manager will be continually amazed that policies he took for com-
mon knowledge are totally unknown by some member of his  team.  Since
his fundamental job is to keep everybody going in the same direction,
his chief daily task will be communication, not decision-making.
                              - Fred Brooks, "The Mythical Man Month"

[U-Boot] [PATCH v2 1/1] OMAP3 SPL: Rework memory initalization and devkit 8000 support

[Tom Rini]

This changes to making the board be responsible for providing a
memory initialization function for SPL and converts the existing
function to provide these services for devkit 8000.  As part of this
suffix the Micron DDR settings with their speed.

Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/omap3/sdrc.c             |   49 ++++++++++-----------------
 arch/arm/include/asm/arch-omap3/mem.h       |   42 ++++------------------
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 board/timll/devkit8000/devkit8000.c         |   25 ++++++++++++++
 4 files changed, 52 insertions(+), 65 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 0dd1955..fd26616 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -111,13 +111,24 @@ u32 get_sdr_cs_offset(u32 cs)
 /*
  * do_sdrc_init -
  *  - Initialize the SDRAM for use.
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *    time depending on memory configuration from stack+global context
+ *  - Code called once in C-Stack only context for CS0 and with early being
+ *    true and a possible 2nd time depending on memory configuration from
+ *    stack+global context.
  */
 void do_sdrc_init(u32 cs, u32 early)
 {
-	struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
+	struct sdrc_actim *sdrc_actim_base0;
+	struct sdrc_actim *sdrc_actim_base1;
 
+	sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+	sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+
+	/*
+	 * When called in the early context this may be SPL and we will
+	 * need to set all of the timings.  This ends up being board
+	 * specific so we call a helper function to take care of this
+	 * for us.
+	 */
 	if (early) {
 		/* reset sdrc controller */
 		writel(SOFTRESET, &sdrc_base->sysconfig);
@@ -128,40 +139,18 @@ void do_sdrc_init(u32 cs, u32 early)
 		/* setup sdrc to ball mux */
 		writel(SDRC_SHARING, &sdrc_base->sharing);
 
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
+		/* Disable Power Down of CKE because of 1 CKE on combo part */
 		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
 				&sdrc_base->power);
 
 		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 		sdelay(0x20000);
-	}
 
-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
- * to prevent this to be build in non-SPL build */
 #ifdef CONFIG_SPL_BUILD
-	/* If we use a SPL there is no x-loader nor config header so we have
-	 * to do the job ourselfs
-	 */
-	if (cs == CS0) {
-		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-		/* General SDRC config */
-		writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
-		writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
-
-		/* AC timings */
-		writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
-		writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
-
-		/* Initialize */
-		writel(CMD_NOP, &sdrc_base->cs[cs].manual);
-		writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
-		writel(V_MR, &sdrc_base->cs[cs].mr);
-	}
+		/* setup timings */
+		board_early_sdrc_init(sdrc_base, sdrc_actim_base0);
 #endif
+	}
 
 	/*
 	 * SDRC timings are set up by x-load or config header
@@ -170,8 +159,6 @@ void do_sdrc_init(u32 cs, u32 early)
 	 * configure CS1 to handle this ommission
 	 */
 	if (cs == CS1) {
-		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-		sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 		writel(readl(&sdrc_base->cs[CS0].mcfg),
 			&sdrc_base->cs[CS1].mcfg);
 		writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 8e28f77..9e86d64 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -138,15 +138,15 @@ enum {
 #define MICRON_CASWIDTH			0x5
 #define MICRON_RASWIDTH			0x2
 #define MICRON_LOCKSTATUS		0x0
-#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
-	(MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
-	(MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
-	(MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
-	(MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
+#define MICRON_V_MCFG_165		((MICRON_LOCKSTATUS << 30) | \
+	(MICRON_RASWIDTH << 24) | (MICRON_CASWIDTH << 20) | \
+	(MICRON_ADDRMUXLEGACY << 19) | (MICRON_RAMSIZE << 8) | \
+	(MICRON_BANKALLOCATION << 6) | (MICRON_B32NOT16 << 4) | \
+	(MICRON_DEEPPD << 3) | (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
 
-#define MICRON_ARCV				2030
-#define MICRON_ARE				0x1
-#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
+#define MICRON_ARCV_165		0x4e2
+#define MICRON_ARE		0x1
+#define MICRON_V_RFR_CTRL_165	((MICRON_ARCV_165 << 8) | (MICRON_ARE))
 
 #define MICRON_BL				0x2
 #define MICRON_SIL				0x0
@@ -194,32 +194,6 @@ enum {
 		(NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
 		(NUMONYX_TWTR_165 << 16))
 
-#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
-#endif
-
-#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
-#define V_MCFG			MICRON_V_MCFG
-#define V_RFR_CTRL		MICRON_V_RFR_CTRL
-#define V_MR			MICRON_V_MR
-#endif
-
-#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
-#endif
-
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
-#error "Please choose the right DDR type in config header"
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
-#error "Please choose the right DDR type in config header"
-#endif
-
 /*
  * GPMC settings -
  * Definitions is as per the following format
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 7b60051..7f2631e 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -38,6 +38,7 @@ void per_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+void board_early_sdrc_init(struct sdrc *, struct sdrc_actim *);
 void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index f50d113..9a0f657 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -138,3 +138,28 @@ int board_eth_init(bd_t *bis)
 	return dm9000_initialize(bis);
 }
 #endif
+
+/*
+ * Routine: board_early_sdrc_init
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings outself on the first bank.
+ */
+void board_early_sdrc_init(struct sdrc *sdrc_base, struct sdrc_actim
+		*sdrc_actim_base0)
+{
+	/* General SDRC config */
+	writel(MICRON_V_MCFG_165, &sdrc_base->cs[CS0].mcfg);
+	writel(MICRON_V_RFR_CTRL_165, &sdrc_base->cs[CS0].rfr_ctrl);
+
+	/* AC timings */
+	writel(MICRON_V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+	writel(MICRON_V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+
+	/* Initialize */
+	writel(CMD_NOP, &sdrc_base->cs[CS0].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[CS0].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[CS0].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[CS0].manual);
+
+	writel(MICRON_V_MR, &sdrc_base->cs[CS0].mr);
+}
-- 
1.7.0.4

[U-Boot] [PATCH 0/2]: OMAP3 SPL updates

[Tom Rini]

On Tue, Oct 4, 2011 at 7:59 AM, Tom Rini <trini@ti.com> wrote:
> Hey all,
>
> The following short series does two things. ?First, it re-works where
> we do memory initalization in SPL for OMAP3 to be board-specific.
> This is needed since in many cases (beagleboard, omap3evm) what timings
> we set depend on what hardware we detect ourself to be running on. ?Second,
> along those same lines what omap_rev_string tells us is doing to be
> board specific as well so provide a weak version in the common omap SPL
> code and lets it be replaced as needed.

Please disregard this version, I need to do a full v3 with the right
set of board_early_sdrc_init, sorry for the noise.

-- 
Tom

[U-Boot] [PATCH 0/2]: OMAP3 SPL updates

[Igor Grinberg]

On 10/07/11 02:28, Tom Rini wrote:
> On Tue, Oct 4, 2011 at 7:59 AM, Tom Rini <trini@ti.com> wrote:
>> Hey all,
>>
>> The following short series does two things.  First, it re-works where
>> we do memory initalization in SPL for OMAP3 to be board-specific.
>> This is needed since in many cases (beagleboard, omap3evm) what timings
>> we set depend on what hardware we detect ourself to be running on.  Second,
>> along those same lines what omap_rev_string tells us is doing to be
>> board specific as well so provide a weak version in the common omap SPL
>> code and lets it be replaced as needed.
> 
> Please disregard this version, I need to do a full v3 with the right
> set of board_early_sdrc_init, sorry for the noise.

While I was looking at the series, I've got similar thoughts.
May be this should be facilitated by providing kind of framework
for the board file only to set the right settings and not duplicate
the board_early_sdrc_init() function (with changed values)?


-- 
Regards,
Igor.

[U-Boot] [PATCH 0/2]: OMAP3 SPL updates

[Tom Rini]

On Sun, Oct 9, 2011 at 2:21 AM, Igor Grinberg <grinberg@compulab.co.il> wrote:
> On 10/07/11 02:28, Tom Rini wrote:
>> On Tue, Oct 4, 2011 at 7:59 AM, Tom Rini <trini@ti.com> wrote:
>>> Hey all,
>>>
>>> The following short series does two things. ?First, it re-works where
>>> we do memory initalization in SPL for OMAP3 to be board-specific.
>>> This is needed since in many cases (beagleboard, omap3evm) what timings
>>> we set depend on what hardware we detect ourself to be running on. ?Second,
>>> along those same lines what omap_rev_string tells us is doing to be
>>> board specific as well so provide a weak version in the common omap SPL
>>> code and lets it be replaced as needed.
>>
>> Please disregard this version, I need to do a full v3 with the right
>> set of board_early_sdrc_init, sorry for the noise.
>
> While I was looking at the series, I've got similar thoughts.
> May be this should be facilitated by providing kind of framework
> for the board file only to set the right settings and not duplicate
> the board_early_sdrc_init() function (with changed values)?

The problem is that what to do is very board specific.  For example
for beagleboard we need to probe the nand driver to see what package
we have and then pick from at least 3, maybe 4 or 5 (I don't have the
code in front of me) settings.  That said, perhaps a function that
takes the series of values that do change would be a little clearer in
the end so I'll give that a spin once I've gotten beagle and omap3evm
spun up again (and maybe finally gotten NAND SPL working there, it
seems to be an omap3-specific issue sadly).

-- 
Tom

[U-Boot] [PATCH 0/2]: OMAP3 SPL updates

[Igor Grinberg]

Hi Tom,

On 10/10/11 05:01, Tom Rini wrote:
> On Sun, Oct 9, 2011 at 2:21 AM, Igor Grinberg <grinberg@compulab.co.il> wrote:
>> On 10/07/11 02:28, Tom Rini wrote:
>>> On Tue, Oct 4, 2011 at 7:59 AM, Tom Rini <trini@ti.com> wrote:
>>>> Hey all,
>>>>
>>>> The following short series does two things.  First, it re-works where
>>>> we do memory initalization in SPL for OMAP3 to be board-specific.
>>>> This is needed since in many cases (beagleboard, omap3evm) what timings
>>>> we set depend on what hardware we detect ourself to be running on.  Second,
>>>> along those same lines what omap_rev_string tells us is doing to be
>>>> board specific as well so provide a weak version in the common omap SPL
>>>> code and lets it be replaced as needed.
>>>
>>> Please disregard this version, I need to do a full v3 with the right
>>> set of board_early_sdrc_init, sorry for the noise.
>>
>> While I was looking at the series, I've got similar thoughts.
>> May be this should be facilitated by providing kind of framework
>> for the board file only to set the right settings and not duplicate
>> the board_early_sdrc_init() function (with changed values)?
> 
> The problem is that what to do is very board specific.  For example
> for beagleboard we need to probe the nand driver to see what package
> we have and then pick from at least 3, maybe 4 or 5 (I don't have the
> code in front of me) settings.

This only means that the framework (or just a common function call)
should be flexible enough to let the board choose the right configuration
in runtime.
After all the DRAM controller should be initialized by the same sequence
just with different values.

> That said, perhaps a function that
> takes the series of values that do change would be a little clearer in
> the end so I'll give that a spin once I've gotten beagle and omap3evm
> spun up again (and maybe finally gotten NAND SPL working there, it
> seems to be an omap3-specific issue sadly).

How about a something like board_get_dram_params() (defined weak)
implemented by a board file and a call added to current
DRAM controller initialization sequence?
 

-- 
Regards,
Igor.