From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Mon, 10 Oct 2011 15:29:00 -0500 Subject: [U-Boot] [PATCH v2] NAND: davinci: choose correct 1-bit h/w ECC reg In-Reply-To: References: Message-ID: <4E93558C.1070602@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/26/2011 11:02 AM, Laurence Withers wrote: > In nand_davinci_readecc(), select the correct NANDFECC register based > on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. > This allows 1-bit hardware ECC to work with chip select other than CS2. > > Note this now matches the usage in nand_davinci_enable_hwecc(), which > already had the correct handling, and allows refactoring to a single > function encapsulating the register read. > > Without this fix, writing NAND pages to a chip not wired to CS2 would > result in in the ECC calculation always returning FFFFFF for each > 512-byte segment, and reading back a correctly written page (one with > ECC intact) would always fail. With this fix, the ECC is written and > verified correctly. > > Signed-off-by: Laurence Withers > --- > Changes for v2: > Add Signed-off-by to commit message. > --- > drivers/mtd/nand/davinci_nand.c | 26 +++++++++++++------------- > 1 files changed, 13 insertions(+), 13 deletions(-) Applied to u-boot-nand-flash -Scott