* [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx
2011-10-11 13:51 [U-Boot] [PATCH 0/5] ARM:AM33XX: Basic support for AM33xx platform Chandan Nath
@ 2011-10-11 13:51 ` Chandan Nath
2011-10-11 16:06 ` Tom Rini
2011-10-11 13:51 ` [U-Boot] [PATCH 2/5] ARM:AM33XX: Add clock definitions Chandan Nath
` (3 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Chandan Nath @ 2011-10-11 13:51 UTC (permalink / raw)
To: u-boot
This patch adds basic support for AM33xx which is based on ARMV7
Cortex A8 CPU.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
---
arch/arm/cpu/armv7/am33xx/Makefile | 44 +++++++
arch/arm/cpu/armv7/am33xx/lowlevel_init.S | 72 ++++++++++
arch/arm/cpu/armv7/am33xx/sys_info.c | 130 +++++++++++++++++++
arch/arm/include/asm/arch-am33xx/cpu.h | 186 +++++++++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/hardware.h | 84 ++++++++++++
5 files changed, 516 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/Makefile
create mode 100644 arch/arm/cpu/armv7/am33xx/lowlevel_init.S
create mode 100644 arch/arm/cpu/armv7/am33xx/sys_info.c
create mode 100644 arch/arm/include/asm/arch-am33xx/cpu.h
create mode 100644 arch/arm/include/asm/arch-am33xx/hardware.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
new file mode 100644
index 0000000..498df78
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+
+COBJS += sys_info.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/am33xx/lowlevel_init.S b/arch/arm/cpu/armv7/am33xx/lowlevel_init.S
new file mode 100644
index 0000000..09fd945
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/lowlevel_init.S
@@ -0,0 +1,72 @@
+/*
+ * lowlevel_init.S
+ *
+ * AM33XX low level initialization.
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Initial Code by:
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+_mark1:
+ .word mark1
+_lowlevel_init1:
+ .word lowlevel_init
+_s_init_start:
+ .word s_init_start
+
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
+
+/*****************************************************************************
+ * lowlevel_init: - Platform low level init.
+ ****************************************************************************/
+.globl lowlevel_init
+lowlevel_init:
+
+ /* The link register is saved in ip by start.S */
+ mov r6, ip
+ /* check if we are already running from RAM */
+ ldr r2, _lowlevel_init1
+ ldr r3, _TEXT_BASE
+ sub r4, r2, r3
+ sub r0, pc, r4
+ ldr sp, SRAM_STACK
+mark1:
+ ldr r5, _mark1
+ sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */
+ sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */
+ mov r10, #0x0 /* r10 has in_ddr used by s_init() */
+
+ ands r0, r0, #0xC0000000
+ /* MSB 2 bits <> 0 then we are in ocmc or DDR */
+ cmp r0, #0x80000000
+ bne s_init_start
+ mov r10, #0x01
+ b s_init_start
+
+s_init_start:
+ mov r0, r10 /* passing in_ddr in r0 */
+ bl s_init
+ /* back to arch calling code */
+ mov pc, r6
+ /* the literal pools origin */
+ .ltorg
+
+SRAM_STACK:
+ /* Place stack at the top */
+ .word (SRAM0_START + SRAM0_SIZE - ROM_CODE_SIZE - 4)
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
new file mode 100644
index 0000000..507b618
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -0,0 +1,130 @@
+/*
+ * sys_info.c
+ *
+ * System information functions
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
+
+/**
+ * get_cpu_rev(void) - extract rev info
+ */
+u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+
+ id = readl(DEVICE_ID);
+ rev = (id >> 28) & 0xff;
+
+ return rev;
+}
+
+/**
+ * get_cpu_type(void) - extract cpu info
+ */
+u32 get_cpu_type(void)
+{
+ u32 id = 0;
+ u32 partnum;
+
+ id = readl(DEVICE_ID);
+ partnum = (id >> 12) & 0xffff;
+
+ return partnum;
+}
+
+/**
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ */
+u32 get_board_rev(void)
+{
+ return BOARD_REV_ID;
+}
+
+/**
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+ int mode;
+ mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+ return mode >>= 8;
+}
+
+/**
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ */
+u32 get_sysboot_value(void)
+{
+ int mode;
+ mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+ return mode;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/**
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ char *cpu_s, *sec_s;
+ int arm_freq, ddr_freq;
+
+ switch (get_cpu_type()) {
+ case AM335X:
+ cpu_s = "AM335X";
+ break;
+ default:
+ cpu_s = "Unknown cpu type";
+ break;
+ }
+
+ switch (get_device_type()) {
+ case TST_DEVICE:
+ sec_s = "TST";
+ break;
+ case EMU_DEVICE:
+ sec_s = "EMU";
+ break;
+ case HS_DEVICE:
+ sec_s = "HS";
+ break;
+ case GP_DEVICE:
+ sec_s = "GP";
+ break;
+ default:
+ sec_s = "?";
+ }
+
+ printf("AM%s-%s rev %d\n",
+ cpu_s, sec_s, get_cpu_rev());
+
+ /* TODO: Print ARM and DDR frequencies */
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
new file mode 100644
index 0000000..cc937ac
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -0,0 +1,186 @@
+/*
+ * cpu.h
+ *
+ * AM33xx specific header file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _AM33XX_CPU_H
+#define _AM33XX_CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+#include <common.h>
+
+#define BIT(x) (1 << x)
+#define CL_BIT(x) (0 << x)
+
+/* Timer register bits */
+#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
+#define TCLR_AR BIT(1) /* Auto reload */
+#define TCLR_PRE BIT(5) /* Pre-scaler enable */
+#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
+#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
+
+/* device type */
+#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
+/* cpu-id for AM33XX family */
+#define AM335X 0xB944
+#define DEVICE_ID 0x44E10600
+
+/* This gives the status of the boot mode pins on the evm */
+#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
+ | BIT(3) | BIT(4))
+
+/* Encapsulating core pll registers */
+struct cm_wkuppll {
+ unsigned int wkclkstctrl; /* offset 0x00 */
+ unsigned int wkctrlclkctrl; /* offset 0x04 */
+ unsigned int resv1[1];
+ unsigned int wkl4wkclkctrl; /* offset 0x0c */
+ unsigned int resv2[4];
+ unsigned int idlestdpllmpu; /* offset 0x20 */
+ unsigned int resv3[2];
+ unsigned int clkseldpllmpu; /* offset 0x2c */
+ unsigned int resv4[1];
+ unsigned int idlestdpllddr; /* offset 0x34 */
+ unsigned int resv5[2];
+ unsigned int clkseldpllddr; /* offset 0x40 */
+ unsigned int resv6[4];
+ unsigned int clkseldplldisp; /* offset 0x54 */
+ unsigned int resv7[1];
+ unsigned int idlestdpllcore; /* offset 0x5c */
+ unsigned int resv8[2];
+ unsigned int clkseldpllcore; /* offset 0x68 */
+ unsigned int resv9[1];
+ unsigned int idlestdpllper; /* offset 0x70 */
+ unsigned int resv10[3];
+ unsigned int divm4dpllcore; /* offset 0x80 */
+ unsigned int divm5dpllcore; /* offset 0x84 */
+ unsigned int clkmoddpllmpu; /* offset 0x88 */
+ unsigned int clkmoddpllper; /* offset 0x8c */
+ unsigned int clkmoddpllcore; /* offset 0x90 */
+ unsigned int clkmoddpllddr; /* offset 0x94 */
+ unsigned int clkmoddplldisp; /* offset 0x98 */
+ unsigned int clkseldpllper; /* offset 0x9c */
+ unsigned int divm2dpllddr; /* offset 0xA0 */
+ unsigned int divm2dplldisp; /* offset 0xA4 */
+ unsigned int divm2dpllmpu; /* offset 0xA8 */
+ unsigned int divm2dpllper; /* offset 0xAC */
+ unsigned int resv11[1];
+ unsigned int wkup_uart0ctrl; /* offset 0xB4 */
+ unsigned int resv12[8];
+ unsigned int divm6dpllcore; /* offset 0xD8 */
+};
+
+/**
+ * Encapsulating peripheral functional clocks
+ * pll registers
+ */
+struct cm_perpll {
+ unsigned int l4lsclkstctrl; /* offset 0x00 */
+ unsigned int l3sclkstctrl; /* offset 0x04 */
+ unsigned int l4fwclkstctrl; /* offset 0x08 */
+ unsigned int l3clkstctrl; /* offset 0x0c */
+ unsigned int resv1[6];
+ unsigned int emifclkctrl; /* offset 0x28 */
+ unsigned int ocmcramclkctrl; /* offset 0x2c */
+ unsigned int resv2[12];
+ unsigned int l4lsclkctrl; /* offset 0x60 */
+ unsigned int l4fwclkctrl; /* offset 0x64 */
+ unsigned int resv3[6];
+ unsigned int timer2clkctrl; /* offset 0x80 */
+ unsigned int resv4[19];
+ unsigned int emiffwclkctrl; /* offset 0xD0 */
+ unsigned int resv5[2];
+ unsigned int l3instrclkctrl; /* offset 0xDC */
+ unsigned int l3clkctrl; /* Offset 0xE0 */
+ unsigned int resv6[14];
+ unsigned int l4hsclkstctrl; /* offset 0x11C */
+ unsigned int l4hsclkctrl; /* offset 0x120 */
+};
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+ unsigned int resv1[2];
+ unsigned int clktimer2clk; /* offset 0x08 */
+};
+
+/* Watchdog timer registers */
+struct wd_timer {
+ unsigned int resv1[4];
+ unsigned int wdtwdsc; /* offset 0x010 */
+ unsigned int wdtwdst; /* offset 0x014 */
+ unsigned int wdtwisr; /* offset 0x018 */
+ unsigned int wdtwier; /* offset 0x01C */
+ unsigned int wdtwwer; /* offset 0x020 */
+ unsigned int wdtwclr; /* offset 0x024 */
+ unsigned int wdtwcrr; /* offset 0x028 */
+ unsigned int wdtwldr; /* offset 0x02C */
+ unsigned int wdtwtgr; /* offset 0x030 */
+ unsigned int wdtwwps; /* offset 0x034 */
+ unsigned int resv2[3];
+ unsigned int wdtwdly; /* offset 0x044 */
+ unsigned int wdtwspr; /* offset 0x048 */
+ unsigned int resv3[1];
+ unsigned int wdtwqeoi; /* offset 0x050 */
+ unsigned int wdtwqstar; /* offset 0x054 */
+ unsigned int wdtwqsta; /* offset 0x058 */
+ unsigned int wdtwqens; /* offset 0x05C */
+ unsigned int wdtwqenc; /* offset 0x060 */
+ unsigned int resv4[39];
+ unsigned int wdt_unfr; /* offset 0x100 */
+};
+
+/* Timer Registers */
+struct timer_reg {
+ unsigned int resv1[4];
+ unsigned int tiocpcfgreg; /* offset 0x10 */
+ unsigned int resv2[9];
+ unsigned int tclrreg; /* offset 0x38 */
+ unsigned int tcrrreg; /* offset 0x3C */
+ unsigned int tldrreg; /* offset 0x40 */
+ unsigned int resv3[4];
+ unsigned int tsicrreg; /* offset 0x54 */
+};
+
+/* UART Registers */
+struct uart_sys {
+ unsigned int resv1[21];
+ unsigned int uartsyscfg; /* offset 0x54 */
+ unsigned int uartsyssts; /* offset 0x58 */
+};
+
+/* VTP Registers */
+struct vtp_reg {
+ unsigned int vtp0ctrlreg;
+};
+
+/* Control Status Register */
+struct ctrl_stat {
+ unsigned int resv1[16];
+ unsigned int statusreg; /* ofset 0x40 */
+};
+
+void init_timer(void);
+
+#endif /* _AM33XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
new file mode 100644
index 0000000..7c8e05f
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -0,0 +1,84 @@
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_H
+#define __AM33XX_HARDWARE_H
+
+/* Module base addresses */
+#define SRAM0_START 0x402f0400
+#define UART0_BASE 0x44E09000
+
+/* DM Timer base addresses */
+#define DM_TIMER0_BASE 0x4802C000
+#define DM_TIMER1_BASE 0x4802E000
+#define DM_TIMER2_BASE 0x48040000
+#define DM_TIMER3_BASE 0x48042000
+#define DM_TIMER4_BASE 0x48044000
+#define DM_TIMER5_BASE 0x48046000
+#define DM_TIMER6_BASE 0x48048000
+#define DM_TIMER7_BASE 0x4804A000
+
+/* GPIO Base address */
+#define GPIO0_BASE 0x48032000
+#define GPIO1_BASE 0x4804C000
+#define GPIO2_BASE 0x481AC000
+
+/* BCH Error Location Module */
+#define ELM_BASE 0x48080000
+
+/* Watchdog Timer */
+#define WDT_BASE 0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE 0x44E10000
+
+/* PRCM Base Address */
+#define PRCM_BASE 0x44E00000
+
+/* EMIF Base address */
+#define EMIF4_0_CFG_BASE 0x4C000000
+#define EMIF4_1_CFG_BASE 0x4D000000
+#define DMM_BASE 0x4E000000
+
+/* PLL related registers */
+#define CM_PER 0x44E00000
+#define CM_WKUP 0x44E00400
+#define CM_DPLL 0x44E00500
+#define CM_DEVICE 0x44E00700
+#define CM_CEFUSE 0x44E00A00
+#define PRM_DEVICE 0x44E00F00
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR 0x44E10E0C
+
+/* DDR Base address */
+#define DDR_CTRL_ADDR 0x44E10E04
+#define DDR_CONTROL_BASE_ADDR 0x44E11404
+#define DDR_PHY_BASE_ADDR 0x44E12000
+#define DDR_PHY_BASE_ADDR2 0x44E120A4
+
+/* UART */
+#define DEFAULT_UART_BASE UART0_BASE
+
+#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+
+#define SRAM0_SIZE 0x20000
+#define ROM_CODE_SIZE 0x4C00
+
+#endif /* __AM33XX_HARDWARE_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx
2011-10-11 13:51 ` [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx Chandan Nath
@ 2011-10-11 16:06 ` Tom Rini
2011-10-12 10:29 ` Kumar
0 siblings, 1 reply; 18+ messages in thread
From: Tom Rini @ 2011-10-11 16:06 UTC (permalink / raw)
To: u-boot
On Tue, Oct 11, 2011 at 6:51 AM, Chandan Nath <chandan.nath@ti.com> wrote:
> This patch adds basic support for AM33xx which is based on ARMV7
> Cortex A8 CPU.
>
> Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[snip]
> +SRAM_STACK:
> + ? ? ? /* Place stack at the top */
> + ? ? ? .word (SRAM0_START + SRAM0_SIZE - ROM_CODE_SIZE - 4)
[snip]
> +#define SRAM0_SIZE ? ? ? ? ? ? ? ? ? ? 0x20000
> +#define ROM_CODE_SIZE ? ? ? ? ? ? ? ? ?0x4C00
I like that we're defining the ROM_CODE_SIZE here. For consistency
with other platforms we should add LOW_LEVEL_SRAM_STACK to this
calculation. Thanks!
--
Tom
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx
2011-10-11 16:06 ` Tom Rini
@ 2011-10-12 10:29 ` Kumar
2011-10-12 14:07 ` Tom Rini
0 siblings, 1 reply; 18+ messages in thread
From: Kumar @ 2011-10-12 10:29 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com]
> Sent: Tuesday, October 11, 2011 9:37 PM
> To: Kumar Nath, Chandan
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx
>
> On Tue, Oct 11, 2011 at 6:51 AM, Chandan Nath <chandan.nath@ti.com>
> wrote:
> > This patch adds basic support for AM33xx which is based on ARMV7
> > Cortex A8 CPU.
> >
> > Signed-off-by: Chandan Nath <chandan.nath@ti.com>
> [snip]
> > +SRAM_STACK:
> > + ? ? ? /* Place stack at the top */
> > + ? ? ? .word (SRAM0_START + SRAM0_SIZE - ROM_CODE_SIZE - 4)
> [snip]
> > +#define SRAM0_SIZE ? ? ? ? ? ? ? ? ? ? 0x20000
> > +#define ROM_CODE_SIZE ? ? ? ? ? ? ? ? ?0x4C00
>
> I like that we're defining the ROM_CODE_SIZE here. For consistency
> with other platforms we should add LOW_LEVEL_SRAM_STACK to this
> calculation. Thanks!
>
To maintain the consistency with other platform, I will use LOW_LEVEL_SRAM_STACK
instead of this calculation. This will be addressed in the next version of this patch set.
> --
> Tom
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx
2011-10-12 10:29 ` Kumar
@ 2011-10-12 14:07 ` Tom Rini
0 siblings, 0 replies; 18+ messages in thread
From: Tom Rini @ 2011-10-12 14:07 UTC (permalink / raw)
To: u-boot
On Wed, Oct 12, 2011 at 3:29 AM, Kumar Nath, Chandan
<chandan.nath@ti.com> wrote:
>> -----Original Message-----
>> From: Tom Rini [mailto:tom.rini at gmail.com]
>> Sent: Tuesday, October 11, 2011 9:37 PM
>> To: Kumar Nath, Chandan
>> Cc: u-boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx
>>
>> On Tue, Oct 11, 2011 at 6:51 AM, Chandan Nath <chandan.nath@ti.com>
>> wrote:
>> > This patch adds basic support for AM33xx which is based on ARMV7
>> > Cortex A8 CPU.
>> >
>> > Signed-off-by: Chandan Nath <chandan.nath@ti.com>
>> [snip]
>> > +SRAM_STACK:
>> > + ? ? ? /* Place stack at the top */
>> > + ? ? ? .word (SRAM0_START + SRAM0_SIZE - ROM_CODE_SIZE - 4)
>> [snip]
>> > +#define SRAM0_SIZE ? ? ? ? ? ? ? ? ? ? 0x20000
>> > +#define ROM_CODE_SIZE ? ? ? ? ? ? ? ? ?0x4C00
>>
>> I like that we're defining the ROM_CODE_SIZE here. ?For consistency
>> with other platforms we should add LOW_LEVEL_SRAM_STACK to this
>> calculation. ?Thanks!
>>
>
> To maintain the consistency with other platform, I will use LOW_LEVEL_SRAM_STACK
> instead of this calculation. This will be addressed in the next version of this patch set.
To be clear, I'm saying we should define LOW_LEVEL_SRAM_STACK to this
calculation. Thanks again.
--
Tom
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 2/5] ARM:AM33XX: Add clock definitions
2011-10-11 13:51 [U-Boot] [PATCH 0/5] ARM:AM33XX: Basic support for AM33xx platform Chandan Nath
2011-10-11 13:51 ` [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx Chandan Nath
@ 2011-10-11 13:51 ` Chandan Nath
2011-10-11 13:51 ` [U-Boot] [PATCH 3/5] ARM:AM33XX: Add emif/ddr support Chandan Nath
` (2 subsequent siblings)
4 siblings, 0 replies; 18+ messages in thread
From: Chandan Nath @ 2011-10-11 13:51 UTC (permalink / raw)
To: u-boot
This patch adds basic clock definition of am33xx SoC.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
---
arch/arm/cpu/armv7/am33xx/Makefile | 1 +
arch/arm/cpu/armv7/am33xx/clock.c | 273 ++++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/clock.h | 24 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 55 +++++
4 files changed, 353 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
create mode 100644 arch/arm/include/asm/arch-am33xx/clock.h
create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 498df78..fc25587 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,6 +18,7 @@ LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
+COBJS += clock.o
COBJS += sys_info.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 0000000..4ca6c45
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,273 @@
+/*
+ * clock.c
+ *
+ * clocks for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define PRCM_MOD_EN 0x2
+#define PRCM_FORCE_WAKEUP 0x2
+
+#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
+#define PRCM_L3_GCLK_ACTIVITY BIT(4)
+
+#define PLL_BYPASS_MODE 0x4
+#define ST_MN_BYPASS 0x00000100
+#define ST_DPLL_CLK 0x00000001
+#define CLK_SEL_MASK 0x7ffff
+#define CLK_DIV_MASK 0x1f
+#define CLK_DIV2_MASK 0x7f
+#define CLK_SEL_SHIFT 0x8
+#define CLK_MODE_SEL 0x7
+#define CLK_MODE_MASK 0xfffffff8
+#define CLK_DIV_SEL 0xFFFFFFE0
+
+
+const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+
+static void enable_interface_clocks(void)
+{
+ /* Enable all the Interconnect Modules */
+ writel(PRCM_MOD_EN, &cmper->l3clkctrl);
+ while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
+ ;
+
+ writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
+ while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
+ ;
+
+ writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
+ while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
+ ;
+
+ writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
+ while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
+ ;
+
+ writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
+ while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
+ ;
+
+ writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
+ while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
+ ;
+}
+
+/*
+ * Force power domain wake up transition
+ * Ensure that the corresponding interface clock is active before
+ * using the peripheral
+ */
+static void power_domain_wkup_transition(void)
+{
+ writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
+ writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
+ writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
+ writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
+ writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
+}
+
+/*
+ * Enable the peripheral clock for required peripherals
+ */
+static void enable_per_clocks(void)
+{
+ /* Enable the control module though RBL would have done it*/
+ writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
+ while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* Enable the module clock */
+ writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
+ while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* UART0 */
+ writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
+ while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
+ ;
+}
+
+static void mpu_pll_config(void)
+{
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddpllmpu);
+ clksel = readl(&cmwkup->clkseldpllmpu);
+ div_m2 = readl(&cmwkup->divm2dpllmpu);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
+ while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
+ ;
+
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+ writel(clksel, &cmwkup->clkseldpllmpu);
+
+ div_m2 = div_m2 & ~CLK_DIV_MASK;
+ div_m2 = div_m2 | MPUPLL_M2;
+ writel(div_m2, &cmwkup->divm2dpllmpu);
+
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllmpu);
+
+ while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
+ ;
+}
+
+static void core_pll_config(void)
+{
+ u32 clkmode, clksel, div_m4, div_m5, div_m6;
+
+ clkmode = readl(&cmwkup->clkmoddpllcore);
+ clksel = readl(&cmwkup->clkseldpllcore);
+ div_m4 = readl(&cmwkup->divm4dpllcore);
+ div_m5 = readl(&cmwkup->divm5dpllcore);
+ div_m6 = readl(&cmwkup->divm6dpllcore);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
+
+ while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
+ ;
+
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
+ writel(clksel, &cmwkup->clkseldpllcore);
+
+ div_m4 = div_m4 & ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4;
+ writel(div_m4, &cmwkup->divm4dpllcore);
+
+ div_m5 = div_m5 & ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5;
+ writel(div_m5, &cmwkup->divm5dpllcore);
+
+ div_m6 = div_m6 & ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6;
+ writel(div_m6, &cmwkup->divm6dpllcore);
+
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllcore);
+
+ while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+ ;
+}
+
+static void per_pll_config(void)
+{
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddpllper);
+ clksel = readl(&cmwkup->clkseldpllper);
+ div_m2 = readl(&cmwkup->divm2dpllper);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
+
+ while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
+ ;
+
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
+ writel(clksel, &cmwkup->clkseldpllper);
+
+ div_m2 = div_m2 & ~CLK_DIV2_MASK;
+ div_m2 = div_m2 | PERPLL_M2;
+ writel(div_m2, &cmwkup->divm2dpllper);
+
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllper);
+
+ while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
+ ;
+}
+
+static void ddr_pll_config(void)
+{
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddpllddr);
+ clksel = readl(&cmwkup->clkseldpllddr);
+ div_m2 = readl(&cmwkup->divm2dpllddr);
+
+ /* Set the PLL to bypass Mode */
+ clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
+ writel(clkmode, &cmwkup->clkmoddpllddr);
+
+ /* Wait till bypass mode is enabled */
+ while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
+ != ST_MN_BYPASS)
+ ;
+
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+ writel(clksel, &cmwkup->clkseldpllddr);
+
+ div_m2 = div_m2 & CLK_DIV_SEL;
+ div_m2 = div_m2 | DDRPLL_M2;
+ writel(div_m2, &cmwkup->divm2dpllddr);
+
+ clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllddr);
+
+ /* Wait till dpll is locked */
+ while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
+ ;
+}
+
+void enable_emif_clocks(void)
+{
+ /* Enable the EMIF_FW Functional clock */
+ writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
+ /* Enable EMIF0 Clock */
+ writel(PRCM_MOD_EN, &cmper->emifclkctrl);
+ /* Poll for emif_gclk & L3_G clock are active */
+ while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
+ PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
+ PRCM_L3_GCLK_ACTIVITY))
+ ;
+ /* Poll if module is functional */
+ while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
+ ;
+}
+
+/*
+ * Configure the PLL/PRCM for necessary peripherals
+ */
+void pll_init()
+{
+ mpu_pll_config();
+ core_pll_config();
+ per_pll_config();
+ ddr_pll_config();
+
+ /* Enable the required interconnect clocks */
+ enable_interface_clocks();
+
+ /* Power domain wake up transition */
+ power_domain_wkup_transition();
+
+ /* Enable the required peripherals */
+ enable_per_clocks();
+}
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
new file mode 100644
index 0000000..872ff82
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -0,0 +1,24 @@
+/*
+ * clock.h
+ *
+ * clock header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#include <asm/arch/clocks_am33xx.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
new file mode 100644
index 0000000..abc5b6b
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -0,0 +1,55 @@
+/*
+ * clocks_am33xx.h
+ *
+ * AM33xx clock define
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCKS_AM33XX_H_
+#define _CLOCKS_AM33XX_H_
+
+#define OSC 24
+
+/* MAIN PLL Fdll = 550 MHZ, */
+#define MPUPLL_M 550
+#define MPUPLL_N 23
+#define MPUPLL_M2 1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M 1000
+#define COREPLL_N 23
+
+#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M 960
+#define PERPLL_N 23
+#define PERPLL_M2 5
+
+/* DDR Freq is 266 MHZ for now */
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+#define DDRPLL_M 266
+#define DDRPLL_N 23
+#define DDRPLL_M2 1
+
+extern void pll_init(void);
+extern void enable_emif_clocks(void);
+
+#endif /* endif _CLOCKS_AM33XX_H_ */
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 3/5] ARM:AM33XX: Add emif/ddr support
2011-10-11 13:51 [U-Boot] [PATCH 0/5] ARM:AM33XX: Basic support for AM33xx platform Chandan Nath
2011-10-11 13:51 ` [U-Boot] [PATCH 1/5] ARM:AM33XX: Added support for AM33xx Chandan Nath
2011-10-11 13:51 ` [U-Boot] [PATCH 2/5] ARM:AM33XX: Add clock definitions Chandan Nath
@ 2011-10-11 13:51 ` Chandan Nath
2011-10-11 13:51 ` [U-Boot] [PATCH 4/5] ARM:AM33XX: Added timer support Chandan Nath
2011-10-11 13:51 ` [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM Chandan Nath
4 siblings, 0 replies; 18+ messages in thread
From: Chandan Nath @ 2011-10-11 13:51 UTC (permalink / raw)
To: u-boot
This patch adds AM33xx emif/ddr support along with board specific
defines.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
---
arch/arm/cpu/armv7/am33xx/Makefile | 3 +
arch/arm/cpu/armv7/am33xx/ddr.c | 147 ++++++++++++++
arch/arm/cpu/armv7/am33xx/emif4.c | 201 ++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 264 ++++++++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/sys_proto.h | 39 ++++
5 files changed, 654 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/ddr.c
create mode 100644 arch/arm/cpu/armv7/am33xx/emif4.c
create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs.h
create mode 100644 arch/arm/include/asm/arch-am33xx/sys_proto.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index fc25587..7ed6678 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -20,6 +20,9 @@ SOBJS := lowlevel_init.o
COBJS += clock.o
COBJS += sys_info.o
+COBJS += ddr.o
+COBJS += emif4.o
+
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
new file mode 100644
index 0000000..ed982c1
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -0,0 +1,147 @@
+/*
+ * DDR Configuration for AM33xx devices.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated -
+http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/io.h>
+
+/**
+ * Base address for EMIF instances
+ */
+static struct emif_regs *emif_reg = {
+ (struct emif_regs *)EMIF4_0_CFG_BASE};
+
+/**
+ * Base address for DDR instance
+ */
+static struct ddr_regs *ddr_reg[2] = {
+ (struct ddr_regs *)DDR_PHY_BASE_ADDR,
+ (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+
+/**
+ * Base address for ddr io control instances
+ */
+static struct ddr_cmdtctrl *ioctrl_reg = {
+ (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+
+/**
+ * As a convention, all functions here return 0 on success
+ * -1 on failure.
+ */
+
+/**
+ * Configure SDRAM
+ */
+int config_sdram(struct sdram_config *cfg)
+{
+ writel(cfg->sdrcr, &emif_reg->sdrcr);
+ writel(cfg->sdrcr2, &emif_reg->sdrcr2);
+ writel(cfg->refresh, &emif_reg->sdrrcr);
+ writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
+
+ return 0;
+}
+
+/**
+ * Set SDRAM timings
+ */
+int set_sdram_timings(struct sdram_timing *t)
+{
+ writel(t->time1, &emif_reg->sdrtim1);
+ writel(t->time1_sh, &emif_reg->sdrtim1sr);
+ writel(t->time2, &emif_reg->sdrtim2);
+ writel(t->time2_sh, &emif_reg->sdrtim2sr);
+ writel(t->time3, &emif_reg->sdrtim3);
+ writel(t->time3_sh, &emif_reg->sdrtim3sr);
+
+ return 0;
+}
+
+/**
+ * Configure DDR PHY
+ */
+int config_ddr_phy(struct ddr_phy_control *p)
+{
+ writel(p->reg, &emif_reg->ddrphycr);
+ writel(p->reg_sh, &emif_reg->ddrphycsr);
+
+ return 0;
+}
+
+/**
+ * Configure DDR CMD control registers
+ */
+int config_cmd_ctrl(struct cmd_control *cmd)
+{
+ writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
+ writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
+ writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
+ writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
+ writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
+
+ writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
+ writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
+ writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
+ writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
+ writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
+
+ writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
+ writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
+ writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
+ writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
+ writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
+
+ return 0;
+}
+
+/**
+ * Configure DDR DATA registers
+ */
+int config_ddr_data(int macrono, struct ddr_data *data)
+{
+ writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
+ writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
+
+ writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
+ writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
+
+ writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
+ writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
+ writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
+ writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
+
+ writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
+ writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
+
+ writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
+ writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
+
+ writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
+
+ return 0;
+}
+
+int config_io_ctrl(struct ddr_ioctrl *ioctrl)
+{
+ writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
+ writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
+ writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
+ writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
+ writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
new file mode 100644
index 0000000..1318365
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -0,0 +1,201 @@
+/*
+ * emif4.c
+ *
+ * AM33XX emif4 configuration file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
+struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+
+#ifdef CONFIG_AM335X_CONFIG_DDR
+static void data_macro_config(int dataMacroNum)
+{
+ struct ddr_data data;
+
+ data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+ |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
+ data.datardsratio1 = DDR2_RD_DQS>>2;
+ data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+ |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
+ data.datawdsratio1 = DDR2_WR_DQS>>2;
+ data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+ |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
+ data.datawiratio1 = DDR2_PHY_WRLVL>>2;
+ data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+ |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
+ data.datagiratio1 = DDR2_PHY_GATELVL>>2;
+ data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+ |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
+ data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
+ data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+ |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
+ data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
+ data.datadldiff0 = PHY_DLL_LOCK_DIFF;
+
+ config_ddr_data(dataMacroNum, &data);
+}
+
+static void cmd_macro_config(void)
+{
+ struct cmd_control cmd;
+
+ cmd.cmd0csratio = DDR2_RATIO;
+ cmd.cmd0csforce = CMD_FORCE;
+ cmd.cmd0csdelay = CMD_DELAY;
+ cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
+ cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
+
+ cmd.cmd1csratio = DDR2_RATIO;
+ cmd.cmd1csforce = CMD_FORCE;
+ cmd.cmd1csdelay = CMD_DELAY;
+ cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
+ cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
+
+ cmd.cmd2csratio = DDR2_RATIO;
+ cmd.cmd2csforce = CMD_FORCE;
+ cmd.cmd2csdelay = CMD_DELAY;
+ cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
+ cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
+
+ config_cmd_ctrl(&cmd);
+
+}
+
+static void config_vtp(void)
+{
+ writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+ &vtpreg->vtp0ctrlreg);
+ writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+ &vtpreg->vtp0ctrlreg);
+ writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
+ &vtpreg->vtp0ctrlreg);
+
+ /* Poll for READY */
+ while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
+ VTP_CTRL_READY)
+ ;
+}
+
+static void config_emif_ddr2(void)
+{
+ int i;
+ int ret;
+ struct sdram_config cfg;
+ struct sdram_timing tmg;
+ struct ddr_phy_control phyc;
+
+ /*Program EMIF0 CFG Registers*/
+ phyc.reg = EMIF_READ_LATENCY;
+ phyc.reg_sh = EMIF_READ_LATENCY;
+ phyc.reg2 = EMIF_READ_LATENCY;
+
+ tmg.time1 = EMIF_TIM1;
+ tmg.time1_sh = EMIF_TIM1;
+ tmg.time2 = EMIF_TIM2;
+ tmg.time2_sh = EMIF_TIM2;
+ tmg.time3 = EMIF_TIM3;
+ tmg.time3_sh = EMIF_TIM3;
+
+ cfg.sdrcr = EMIF_SDCFG;
+ cfg.sdrcr2 = EMIF_SDCFG;
+ cfg.refresh = 0x00004650;
+ cfg.refresh_sh = 0x00004650;
+
+ /* Program EMIF instance */
+ ret = config_ddr_phy(&phyc);
+ if (ret < 0)
+ printf("Couldn't configure phyc\n");
+
+ ret = config_sdram(&cfg);
+ if (ret < 0)
+ printf("Couldn't configure SDRAM\n");
+
+ ret = set_sdram_timings(&tmg);
+ if (ret < 0)
+ printf("Couldn't configure timings\n");
+
+ /* Delay */
+ for (i = 0; i < 5000; i++)
+ ;
+
+ cfg.refresh = EMIF_SDREF;
+ cfg.refresh_sh = EMIF_SDREF;
+ cfg.sdrcr = EMIF_SDCFG;
+ cfg.sdrcr2 = EMIF_SDCFG;
+
+ ret = config_sdram(&cfg);
+ if (ret < 0)
+ printf("Couldn't configure SDRAM\n");
+}
+
+void config_ddr(void)
+{
+ int data_macro_0 = 0;
+ int data_macro_1 = 1;
+ struct ddr_ioctrl ioctrl;
+
+ enable_emif_clocks();
+
+ config_vtp();
+
+ cmd_macro_config();
+
+ data_macro_config(data_macro_0);
+ data_macro_config(data_macro_1);
+
+ writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
+ writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+
+ ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+
+ config_io_ctrl(&ioctrl);
+
+ writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
+ writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
+
+ config_emif_ddr2();
+}
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
new file mode 100644
index 0000000..9638b4c
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -0,0 +1,264 @@
+/*
+ * ddr_defs.h
+ *
+ * ddr specific header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DDR_DEFS_H
+#define _DDR_DEFS_H
+
+#include <asm/arch/hardware.h>
+
+/* AM335X EMIF Register values */
+#define EMIF_SDMGT 0x80000000
+#define EMIF_SDRAM 0x00004650
+#define EMIF_PHYCFG 0x2
+#define DDR_PHY_RESET (0x1 << 10)
+#define DDR_FUNCTIONAL_MODE_EN 0x1
+#define DDR_PHY_READY (0x1 << 2)
+#define VTP_CTRL_READY (0x1 << 5)
+#define VTP_CTRL_ENABLE (0x1 << 6)
+#define VTP_CTRL_LOCK_EN (0x1 << 4)
+#define VTP_CTRL_START_EN (0x1)
+#define DDR2_RATIO 0x80
+#define CMD_FORCE 0x00
+#define CMD_DELAY 0x00
+
+#define EMIF_READ_LATENCY 0x04
+#define EMIF_TIM1 0x0666B3D6
+#define EMIF_TIM2 0x143731DA
+#define EMIF_TIM3 0x00000347
+#define EMIF_SDCFG 0x43805332
+#define EMIF_SDREF 0x0000081a
+#define DDR2_DLL_LOCK_DIFF 0x0
+#define DDR2_RD_DQS 0x12
+#define DDR2_PHY_FIFO_WE 0x80
+
+#define DDR2_INVERT_CLKOUT 0x00
+#define DDR2_WR_DQS 0x00
+#define DDR2_PHY_WRLVL 0x00
+#define DDR2_PHY_GATELVL 0x00
+#define DDR2_PHY_WR_DATA 0x40
+#define PHY_RANK0_DELAY 0x01
+#define PHY_DLL_LOCK_DIFF 0x0
+#define DDR_IOCTRL_VALUE 0x18B
+
+/**
+ * This structure represents the EMIF registers on AM33XX devices.
+ */
+struct emif_regs {
+ unsigned int sdrrev; /* offset 0x00 */
+ unsigned int sdrstat; /* offset 0x04 */
+ unsigned int sdrcr; /* offset 0x08 */
+ unsigned int sdrcr2; /* offset 0x0C */
+ unsigned int sdrrcr; /* offset 0x10 */
+ unsigned int sdrrcsr; /* offset 0x14 */
+ unsigned int sdrtim1; /* offset 0x18 */
+ unsigned int sdrtim1sr; /* offset 0x1C */
+ unsigned int sdrtim2; /* offset 0x20 */
+ unsigned int sdrtim2sr; /* offset 0x24 */
+ unsigned int sdrtim3; /* offset 0x28 */
+ unsigned int sdrtim3sr; /* offset 0x2C */
+ unsigned int res1[2];
+ unsigned int sdrmcr; /* offset 0x38 */
+ unsigned int sdrmcsr; /* offset 0x3C */
+ unsigned int res2[8];
+ unsigned int sdritr; /* offset 0x60 */
+ unsigned int res3[20];
+ unsigned int ddrphycr; /* offset 0xE4 */
+ unsigned int ddrphycsr; /* offset 0xE8 */
+ unsigned int ddrphycr2; /* offset 0xEC */
+};
+
+/**
+ * Encapsulates DDR PHY control and corresponding shadow registers.
+ */
+struct ddr_phy_control {
+ unsigned long reg;
+ unsigned long reg_sh;
+ unsigned long reg2;
+};
+
+/**
+ * Encapsulates SDRAM timing and corresponding shadow registers.
+ */
+struct sdram_timing {
+ unsigned long time1;
+ unsigned long time1_sh;
+ unsigned long time2;
+ unsigned long time2_sh;
+ unsigned long time3;
+ unsigned long time3_sh;
+};
+
+/**
+ * Encapsulates SDRAM configuration.
+ * (Includes refresh control registers) */
+struct sdram_config {
+ unsigned long sdrcr;
+ unsigned long sdrcr2;
+ unsigned long refresh;
+ unsigned long refresh_sh;
+};
+
+/**
+ * Configure SDRAM
+ */
+int config_sdram(struct sdram_config *cfg);
+
+/**
+ * Set SDRAM timings
+ */
+int set_sdram_timings(struct sdram_timing *val);
+
+/**
+ * Configure DDR PHY
+ */
+int config_ddr_phy(struct ddr_phy_control *cfg);
+
+/**
+ * This structure represents the DDR registers on AM33XX devices.
+ */
+struct ddr_regs {
+ unsigned int resv0[7];
+ unsigned int cm0csratio; /* offset 0x01C */
+ unsigned int cm0csforce; /* offset 0x020 */
+ unsigned int cm0csdelay; /* offset 0x024 */
+ unsigned int cm0dldiff; /* offset 0x028 */
+ unsigned int cm0iclkout; /* offset 0x02C */
+ unsigned int resv1[8];
+ unsigned int cm1csratio; /* offset 0x050 */
+ unsigned int cm1csforce; /* offset 0x054 */
+ unsigned int cm1csdelay; /* offset 0x058 */
+ unsigned int cm1dldiff; /* offset 0x05C */
+ unsigned int cm1iclkout; /* offset 0x060 */
+ unsigned int resv2[8];
+ unsigned int cm2csratio; /* offset 0x084 */
+ unsigned int cm2csforce; /* offset 0x088 */
+ unsigned int cm2csdelay; /* offset 0x08C */
+ unsigned int cm2dldiff; /* offset 0x090 */
+ unsigned int cm2iclkout; /* offset 0x094 */
+ unsigned int resv3[12];
+ unsigned int dt0rdsratio0; /* offset 0x0C8 */
+ unsigned int dt0rdsratio1; /* offset 0x0CC */
+ unsigned int resv4[3];
+ unsigned int dt0wdsratio0; /* offset 0x0DC */
+ unsigned int dt0wdsratio1; /* offset 0x0E0 */
+ unsigned int resv5[3];
+ unsigned int dt0wiratio0; /* offset 0x0F0 */
+ unsigned int dt0wiratio1; /* offset 0x0F4 */
+ unsigned int dt0giratio0; /* offset 0x0FC */
+ unsigned int dt0giratio1; /* offset 0x100 */
+ unsigned int resv6[2];
+ unsigned int dt0fwsratio0; /* offset 0x108 */
+ unsigned int dt0fwsratio1; /* offset 0x10C */
+ unsigned int resv7[5];
+ unsigned int dt0wrsratio0; /* offset 0x120 */
+ unsigned int dt0wrsratio1; /* offset 0x124 */
+ unsigned int resv8[3];
+ unsigned int dt0rdelays0; /* offset 0x134 */
+ unsigned int dt0dldiff0; /* offset 0x138 */
+ unsigned int resv9[39];
+ unsigned int dt1rdelays0; /* offset 0x1D8 */
+};
+
+/**
+ * Encapsulates DDR CMD control registers.
+ */
+struct cmd_control {
+ unsigned long cmd0csratio;
+ unsigned long cmd0csforce;
+ unsigned long cmd0csdelay;
+ unsigned long cmd0dldiff;
+ unsigned long cmd0iclkout;
+ unsigned long cmd1csratio;
+ unsigned long cmd1csforce;
+ unsigned long cmd1csdelay;
+ unsigned long cmd1dldiff;
+ unsigned long cmd1iclkout;
+ unsigned long cmd2csratio;
+ unsigned long cmd2csforce;
+ unsigned long cmd2csdelay;
+ unsigned long cmd2dldiff;
+ unsigned long cmd2iclkout;
+};
+
+/**
+ * Encapsulates DDR DATA registers.
+ */
+struct ddr_data {
+ unsigned long datardsratio0;
+ unsigned long datardsratio1;
+ unsigned long datawdsratio0;
+ unsigned long datawdsratio1;
+ unsigned long datawiratio0;
+ unsigned long datawiratio1;
+ unsigned long datagiratio0;
+ unsigned long datagiratio1;
+ unsigned long datafwsratio0;
+ unsigned long datafwsratio1;
+ unsigned long datawrsratio0;
+ unsigned long datawrsratio1;
+ unsigned long datadldiff0;
+};
+
+/**
+ * Configure DDR CMD control registers
+ */
+int config_cmd_ctrl(struct cmd_control *cmd);
+
+/**
+ * Configure DDR DATA registers
+ */
+int config_ddr_data(int data_macrono, struct ddr_data *data);
+
+/**
+ * This structure represents the DDR io control on AM33XX devices.
+ */
+struct ddr_cmdtctrl {
+ unsigned int resv1[1];
+ unsigned int cm0ioctl;
+ unsigned int cm1ioctl;
+ unsigned int cm2ioctl;
+ unsigned int resv2[12];
+ unsigned int dt0ioctl;
+ unsigned int dt1ioctl;
+};
+
+/**
+ * Encapsulates DDR CMD & DATA io control registers.
+ */
+struct ddr_ioctrl {
+ unsigned long cmd1ctl;
+ unsigned long cmd2ctl;
+ unsigned long cmd3ctl;
+ unsigned long data1ctl;
+ unsigned long data2ctl;
+};
+
+/**
+ * Configure DDR io control registers
+ */
+int config_io_ctrl(struct ddr_ioctrl *ioctrl);
+
+struct ddr_ctrl {
+ unsigned int ddrioctrl;
+ unsigned int resv1[325];
+ unsigned int ddrckectrl;
+};
+
+void config_ddr(void);
+
+#endif /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
new file mode 100644
index 0000000..1e265c6
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -0,0 +1,39 @@
+/*
+ * sys_proto.h
+ *
+ * System information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#define BOARD_REV_ID 0x0
+struct {
+ u32 board_type_v1;
+ u32 board_type_v2;
+ u32 mtype;
+ char *board_string;
+ char *nand_string;
+} board_sysinfo;
+
+u32 get_cpu_rev(void);
+u32 get_sysboot_value(void);
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void);
+#endif
+
+u32 get_device_type(void);
+#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 4/5] ARM:AM33XX: Added timer support
2011-10-11 13:51 [U-Boot] [PATCH 0/5] ARM:AM33XX: Basic support for AM33xx platform Chandan Nath
` (2 preceding siblings ...)
2011-10-11 13:51 ` [U-Boot] [PATCH 3/5] ARM:AM33XX: Add emif/ddr support Chandan Nath
@ 2011-10-11 13:51 ` Chandan Nath
2011-10-11 16:04 ` Tom Rini
2011-10-11 13:51 ` [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM Chandan Nath
4 siblings, 1 reply; 18+ messages in thread
From: Chandan Nath @ 2011-10-11 13:51 UTC (permalink / raw)
To: u-boot
This patch adds timer support for AM33xx platform.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
---
Makefile | 3 +++
arch/arm/cpu/armv7/omap-common/Makefile | 2 ++
arch/arm/cpu/armv7/omap-common/timer.c | 1 +
arch/arm/include/asm/arch-am33xx/cpu.h | 27 +++++++++++++++++++++++++++
4 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
index 77140eb..60b285c 100644
--- a/Makefile
+++ b/Makefile
@@ -279,6 +279,9 @@ LIBS += lib/libfdt/libfdt.o
LIBS += api/libapi.o
LIBS += post/libpost.o
+ifeq ($(SOC),am33xx)
+LIBS += $(CPUDIR)/omap-common/libomap-common.o
+endif
ifeq ($(SOC),omap3)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index ea9f8ec..7311591 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -29,7 +29,9 @@ SOBJS := reset.o
COBJS := timer.o
COBJS += utils.o
+ifdef CONFIG_OMAP
COBJS += gpio.o
+endif
ifdef CONFIG_SPL_BUILD
COBJS += spl.o
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
index 9f8bc93..a00c242 100644
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -34,6 +34,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index cc937ac..3b9b1ca 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -163,6 +163,33 @@ struct timer_reg {
unsigned int tsicrreg; /* offset 0x54 */
};
+/* Timer 32 bit registers */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+ unsigned int tidr; /* offset 0x00 */
+ unsigned int res1[0xc];
+ unsigned int tiocp_cfg; /* offset 0x10 */
+ unsigned int res2[0xc];
+ unsigned int tier; /* offset 0x20 */
+ unsigned int tistatr; /* offset 0x24 */
+ unsigned int tistat; /* offset 0x28 */
+ unsigned int tisr; /* offset 0x2c */
+ unsigned int tcicr; /* offset 0x30 */
+ unsigned int twer; /* offset 0x34 */
+ unsigned int tclr; /* offset 0x38 */
+ unsigned int tcrr; /* offset 0x3c */
+ unsigned int tldr; /* offset 0x40 */
+ unsigned int ttgr; /* offset 0x44 */
+ unsigned int twpc; /* offset 0x48 */
+ unsigned int tmar; /* offset 0x4c */
+ unsigned int tcar1; /* offset 0x50 */
+ unsigned int tscir; /* offset 0x54 */
+ unsigned int tcar2; /* offset 0x58 */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
/* UART Registers */
struct uart_sys {
unsigned int resv1[21];
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 4/5] ARM:AM33XX: Added timer support
2011-10-11 13:51 ` [U-Boot] [PATCH 4/5] ARM:AM33XX: Added timer support Chandan Nath
@ 2011-10-11 16:04 ` Tom Rini
2011-10-12 10:25 ` Kumar
0 siblings, 1 reply; 18+ messages in thread
From: Tom Rini @ 2011-10-11 16:04 UTC (permalink / raw)
To: u-boot
On Tue, Oct 11, 2011 at 6:51 AM, Chandan Nath <chandan.nath@ti.com> wrote:
> This patch adds timer support for AM33xx platform.
>
> Signed-off-by: Chandan Nath <chandan.nath@ti.com>
> ---
> ?Makefile ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?3 +++
> ?arch/arm/cpu/armv7/omap-common/Makefile | ? ?2 ++
> ?arch/arm/cpu/armv7/omap-common/timer.c ?| ? ?1 +
We shouldn't need to change timer.c. am335x_evm.h should be including
both <asm/arch/cpu.h> and <asm/arch/hardware.h>. Thanks.
--
Tom
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 4/5] ARM:AM33XX: Added timer support
2011-10-11 16:04 ` Tom Rini
@ 2011-10-12 10:25 ` Kumar
0 siblings, 0 replies; 18+ messages in thread
From: Kumar @ 2011-10-12 10:25 UTC (permalink / raw)
To: u-boot
Tom,
> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com]
> Sent: Tuesday, October 11, 2011 9:34 PM
> To: Kumar Nath, Chandan
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 4/5] ARM:AM33XX: Added timer support
>
> On Tue, Oct 11, 2011 at 6:51 AM, Chandan Nath <chandan.nath@ti.com>
> wrote:
> > This patch adds timer support for AM33xx platform.
> >
> > Signed-off-by: Chandan Nath <chandan.nath@ti.com>
> > ---
> > ?Makefile ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?3 +++
> > ?arch/arm/cpu/armv7/omap-common/Makefile | ? ?2 ++
> > ?arch/arm/cpu/armv7/omap-common/timer.c ?| ? ?1 +
>
> We shouldn't need to change timer.c. am335x_evm.h should be including
> both <asm/arch/cpu.h> and <asm/arch/hardware.h>. Thanks.
>
I will address this in the next version of patch set.
<asm/arch/cpu.h> and <asm/arch/hardware.h> will be included in am335x_evm.h
> --
> Tom
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-11 13:51 [U-Boot] [PATCH 0/5] ARM:AM33XX: Basic support for AM33xx platform Chandan Nath
` (3 preceding siblings ...)
2011-10-11 13:51 ` [U-Boot] [PATCH 4/5] ARM:AM33XX: Added timer support Chandan Nath
@ 2011-10-11 13:51 ` Chandan Nath
2011-10-11 16:09 ` Tom Rini
` (2 more replies)
4 siblings, 3 replies; 18+ messages in thread
From: Chandan Nath @ 2011-10-11 13:51 UTC (permalink / raw)
To: u-boot
This patch adds basic support for booting the board.
This patch adds support for the UART necessary to
get to the u-boot prompt.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
---
Support for additional peripherals depends on this patchset.
Will be posting them soon.
arch/arm/cpu/armv7/am33xx/Makefile | 2 +-
arch/arm/cpu/armv7/am33xx/board.c | 66 +++++++++
board/ti/am335x/Makefile | 43 ++++++
board/ti/am335x/common_def.h | 24 +++
board/ti/am335x/evm.c | 50 +++++++
board/ti/am335x/mux.c | 278 ++++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
drivers/serial/ns16550.c | 7 +-
include/configs/am335x_evm.h | 121 ++++++++++++++++
9 files changed, 589 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/board.c
create mode 100644 board/ti/am335x/Makefile
create mode 100644 board/ti/am335x/common_def.h
create mode 100644 board/ti/am335x/evm.c
create mode 100644 board/ti/am335x/mux.c
create mode 100644 include/configs/am335x_evm.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 7ed6678..6beafbb 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -22,7 +22,7 @@ COBJS += clock.o
COBJS += sys_info.o
COBJS += ddr.o
COBJS += emif4.o
-
+COBJS += board.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
new file mode 100644
index 0000000..2d6d359
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -0,0 +1,66 @@
+/*
+ * board.c
+ *
+ * Common board functions for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(u32 in_ddr)
+{
+ /* WDT1 is already running when the bootloader gets control
+ * Disable it to avoid "random" resets
+ */
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+
+ /* Setup the PLLs and the clocks for the peripherals */
+#ifdef CONFIG_SETUP_PLL
+ pll_init();
+#endif
+ if (!in_ddr)
+ config_ddr();
+}
+
+/* Initialize timer */
+void init_timer(void)
+{
+ /* Reset the Timer */
+ writel(0x2, (&timerreg->tsicrreg));
+
+ /* Wait until the reset is done */
+ while (readl(&timerreg->tiocpcfgreg) & 1)
+ ;
+
+ /* Start the Timer */
+ writel(0x1, (&timerreg->tclrreg));
+}
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
new file mode 100644
index 0000000..d58b185
--- /dev/null
+++ b/board/ti/am335x/Makefile
@@ -0,0 +1,43 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := evm.o mux.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/am335x/common_def.h b/board/ti/am335x/common_def.h
new file mode 100644
index 0000000..1696d60
--- /dev/null
+++ b/board/ti/am335x/common_def.h
@@ -0,0 +1,24 @@
+/*
+ * common_def.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COMMON_DEF_H__
+#define __COMMON_DEF_H__
+
+extern void enable_uart0_pin_mux(void);
+extern void configure_evm_pin_mux(unsigned char daughter_board_id,
+ unsigned short daughter_board_profile,
+ unsigned char daughter_board_flag);
+
+#endif/*__COMMON_DEF_H__ */
diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c
new file mode 100644
index 0000000..25a3755
--- /dev/null
+++ b/board/ti/am335x/evm.c
@@ -0,0 +1,50 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include "common_def.h"
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+/*
+ * Basic board specific setup
+ */
+int init_basic_setup(void)
+{
+ /* Initialize the Timer */
+ init_timer();
+
+ gd->bd->bi_arch_number = MACH_TYPE_TIAM335EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ enable_uart0_pin_mux();
+ init_basic_setup();
+
+ return 0;
+}
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
new file mode 100644
index 0000000..8f27409
--- /dev/null
+++ b/board/ti/am335x/mux.c
@@ -0,0 +1,278 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include "common_def.h"
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset) \
+ __raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL (0x1 << 6)
+#define RXACTIVE (0x1 << 5)
+#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) val /* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+};
+
+struct module_pin_mux {
+ short reg_offset;
+ unsigned char val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+/*
+ * Configure the pin mux for the module
+ */
+static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+ int i;
+
+ if (!mod_pin_mux)
+ return;
+
+ for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+ MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
diff --git a/boards.cfg b/boards.cfg
index d32ff7e..6d89d49 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -155,6 +155,7 @@ dkb arm arm926ejs - Marvell pantheon
integratorap_cm946es arm arm946es integrator armltd - integratorap
integratorcp_cm946es arm arm946es integrator armltd - integratorcp
ca9x4_ct_vxp arm armv7 vexpress armltd
+am335x_evm arm armv7 am335x ti am33xx
efikamx arm armv7 efikamx - mx5 efikamx:IMX_CONFIG=board/efikamx/imximage.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8eeb48f..71cbdad 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -31,7 +31,8 @@
void NS16550_init (NS16550_t com_port, int baud_divisor)
{
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
-#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
+#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
+ defined(CONFIG_AM33XX)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
@@ -44,7 +45,9 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
serial_out(baud_divisor & 0xff, &com_port->dll);
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
-#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
+#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
+ defined(CONFIG_AM33XX)
+
#if defined(CONFIG_APTIX)
serial_out(3, &com_port->mdr1); /* /13 mode so Aptix 6MHz can hit 115200 */
#else
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
new file mode 100644
index 0000000..b471f12
--- /dev/null
+++ b/include/configs/am335x_evm.h
@@ -0,0 +1,121 @@
+/*
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM335X_EVM_H
+#define __CONFIG_AM335X_EVM_H
+
+#define CONFIG_CMD_MEMORY /* for mtest */
+#undef CONFIG_GZIP
+#undef CONFIG_ZLIB
+#undef CONFIG_SYS_HUSH_PARSER
+#undef CONFIG_CMD_NET
+
+#define CONFIG_SETUP_PLL
+#define CONFIG_AM335X_CONFIG_DDR
+#define CONFIG_ENV_SIZE 0x400
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 * 1024))
+#define CONFIG_SYS_PROMPT "AM335X# "
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=yes\0" \
+ "ramdisk_file=ramdisk.gz\0" \
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for
+ initial data */
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 32
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ + (8 * 1024 * 1024))
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
+#define CONFIG_SYS_HZ 1000 /* 1ms clock */
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
+#define PHYS_DRAM_1_SIZE 0x10000000 /*(0x80000000 / 8) 256 MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_CLK_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK (48000000)
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM4 0x481A6000 /* UART3 on IA BOard */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_TEXT_BASE 0x402f0400
+
+/* Reset control */
+#define PRM_RSTCTRL 0x44E00F00
+#define PRM_RSTCTRL_RESET 0x01
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#endif /* ! __CONFIG_AM335X_EVM_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-11 13:51 ` [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM Chandan Nath
@ 2011-10-11 16:09 ` Tom Rini
2011-10-12 10:30 ` Kumar
2011-10-12 7:53 ` Igor Grinberg
2011-10-12 8:04 ` Igor Grinberg
2 siblings, 1 reply; 18+ messages in thread
From: Tom Rini @ 2011-10-11 16:09 UTC (permalink / raw)
To: u-boot
On Tue, Oct 11, 2011 at 6:51 AM, Chandan Nath <chandan.nath@ti.com> wrote:
> This patch adds basic support for booting the board.
> This patch adds support for the UART necessary to
> get to the u-boot prompt.
>
> Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[snip]
> +/* Reset control */
> +#define PRM_RSTCTRL ? ? ? ? ? ? ? ? ? ?0x44E00F00
> +#define PRM_RSTCTRL_RESET ? ? ? ? ? ? ?0x01
The reset value doesn't change. We should either do #if/#elif/.. in
<asm/arch/cpu.h> or set PRM_RSTCTRL to CONFIG_SYS_PRM_RSTCTRL.
Thanks!
--
Tom
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-11 16:09 ` Tom Rini
@ 2011-10-12 10:30 ` Kumar
0 siblings, 0 replies; 18+ messages in thread
From: Kumar @ 2011-10-12 10:30 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com]
> Sent: Tuesday, October 11, 2011 9:40 PM
> To: Kumar Nath, Chandan
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X
> EVM
>
> On Tue, Oct 11, 2011 at 6:51 AM, Chandan Nath <chandan.nath@ti.com>
> wrote:
> > This patch adds basic support for booting the board.
> > This patch adds support for the UART necessary to
> > get to the u-boot prompt.
> >
> > Signed-off-by: Chandan Nath <chandan.nath@ti.com>
> [snip]
> > +/* Reset control */
> > +#define PRM_RSTCTRL ? ? ? ? ? ? ? ? ? ?0x44E00F00
> > +#define PRM_RSTCTRL_RESET ? ? ? ? ? ? ?0x01
>
> The reset value doesn't change. We should either do #if/#elif/.. in
> <asm/arch/cpu.h> or set PRM_RSTCTRL to CONFIG_SYS_PRM_RSTCTRL.
Ok, I will address this in next patch set version.
> Thanks!
>
> --
> Tom
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-11 13:51 ` [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM Chandan Nath
2011-10-11 16:09 ` Tom Rini
@ 2011-10-12 7:53 ` Igor Grinberg
2011-10-12 10:18 ` Premi, Sanjeev
2011-10-12 11:08 ` Kumar
2011-10-12 8:04 ` Igor Grinberg
2 siblings, 2 replies; 18+ messages in thread
From: Igor Grinberg @ 2011-10-12 7:53 UTC (permalink / raw)
To: u-boot
Hi Chandan,
On 10/11/11 15:51, Chandan Nath wrote:
> This patch adds basic support for booting the board.
> This patch adds support for the UART necessary to
> get to the u-boot prompt.
>
> Signed-off-by: Chandan Nath <chandan.nath@ti.com>
> ---
> Support for additional peripherals depends on this patchset.
> Will be posting them soon.
Please, don't forget to specify the dependencies when you post
the depending patch sets.
[...]
> diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c
> new file mode 100644
> index 0000000..25a3755
> --- /dev/null
> +++ b/board/ti/am335x/evm.c
> @@ -0,0 +1,50 @@
[...]
> +/*
> + * Basic board specific setup
> + */
> +int init_basic_setup(void)
> +{
> + /* Initialize the Timer */
> + init_timer();
> +
> + gd->bd->bi_arch_number = MACH_TYPE_TIAM335EVM;
Please, use the new standard for setting the mach_id.
Check the CONFIG_MACH_TYPE option in the README file.
> +
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + enable_uart0_pin_mux();
> + init_basic_setup();
> +
> + return 0;
> +}
[...]
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-12 7:53 ` Igor Grinberg
@ 2011-10-12 10:18 ` Premi, Sanjeev
2011-10-12 21:19 ` Igor Grinberg
2011-10-12 11:08 ` Kumar
1 sibling, 1 reply; 18+ messages in thread
From: Premi, Sanjeev @ 2011-10-12 10:18 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Igor Grinberg
> Sent: Wednesday, October 12, 2011 1:24 PM
> To: Kumar Nath, Chandan
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for
> TI AM335X EVM
>
> Hi Chandan,
>
> On 10/11/11 15:51, Chandan Nath wrote:
> > This patch adds basic support for booting the board.
> > This patch adds support for the UART necessary to
> > get to the u-boot prompt.
> >
> > Signed-off-by: Chandan Nath <chandan.nath@ti.com>
> > ---
> > Support for additional peripherals depends on this patchset.
> > Will be posting them soon.
>
> Please, don't forget to specify the dependencies when you post
> the depending patch sets.
Igor,
The comment means that there are more patches in the pipeline
that depend on "this" patchset. This patchset doesn't have any
dependency.
~sanjeev
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-12 10:18 ` Premi, Sanjeev
@ 2011-10-12 21:19 ` Igor Grinberg
0 siblings, 0 replies; 18+ messages in thread
From: Igor Grinberg @ 2011-10-12 21:19 UTC (permalink / raw)
To: u-boot
On 10/12/11 12:18, Premi, Sanjeev wrote:
>> -----Original Message-----
>> From: u-boot-bounces at lists.denx.de
>> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Igor Grinberg
>> Sent: Wednesday, October 12, 2011 1:24 PM
>> To: Kumar Nath, Chandan
>> Cc: u-boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for
>> TI AM335X EVM
>>
>> Hi Chandan,
>>
>> On 10/11/11 15:51, Chandan Nath wrote:
>>> This patch adds basic support for booting the board.
>>> This patch adds support for the UART necessary to
>>> get to the u-boot prompt.
>>>
>>> Signed-off-by: Chandan Nath <chandan.nath@ti.com>
>>> ---
>>> Support for additional peripherals depends on this patchset.
>>> Will be posting them soon.
>>
>> Please, don't forget to specify the dependencies when you post
>> the depending patch sets.
>
> Igor,
> The comment means that there are more patches in the pipeline
> that depend on "this" patchset. This patchset doesn't have any
> dependency.
I know it does not. I think you've misunderstood me :)
(or my English is not good enough, which I think is a real problem).
By saying "depending patch sets", I meant the future patchsets that
will depend on the current one.
Technically, it is more important to specify that a patchset depends
on something than there will be patches that depend on the current one. :)
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-12 7:53 ` Igor Grinberg
2011-10-12 10:18 ` Premi, Sanjeev
@ 2011-10-12 11:08 ` Kumar
1 sibling, 0 replies; 18+ messages in thread
From: Kumar @ 2011-10-12 11:08 UTC (permalink / raw)
To: u-boot
Igor,
> > +/*
> > + * Basic board specific setup
> > + */
> > +int init_basic_setup(void)
> > +{
> > + /* Initialize the Timer */
> > + init_timer();
> > +
> > + gd->bd->bi_arch_number = MACH_TYPE_TIAM335EVM;
>
> Please, use the new standard for setting the mach_id.
> Check the CONFIG_MACH_TYPE option in the README file.
>
Yes, I will use CONFIG_MACH_TYPE option for setting mach_id
and will post this in next version of patch set.
> > +
> > + /* address of boot parameters */
> > + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
> > +
> > + return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > + enable_uart0_pin_mux();
> > + init_basic_setup();
> > +
> > + return 0;
> > +}
>
> [...]
>
>
> --
> Regards,
> Igor.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM
2011-10-11 13:51 ` [U-Boot] [PATCH 5/5] ARM:AM33XX: Add support for TI AM335X EVM Chandan Nath
2011-10-11 16:09 ` Tom Rini
2011-10-12 7:53 ` Igor Grinberg
@ 2011-10-12 8:04 ` Igor Grinberg
2 siblings, 0 replies; 18+ messages in thread
From: Igor Grinberg @ 2011-10-12 8:04 UTC (permalink / raw)
To: u-boot
On 10/11/11 15:51, Chandan Nath wrote:
> This patch adds basic support for booting the board.
> This patch adds support for the UART necessary to
> get to the u-boot prompt.
>
> Signed-off-by: Chandan Nath <chandan.nath@ti.com>
> ---
> Support for additional peripherals depends on this patchset.
> Will be posting them soon.
>
> arch/arm/cpu/armv7/am33xx/Makefile | 2 +-
> arch/arm/cpu/armv7/am33xx/board.c | 66 +++++++++
> board/ti/am335x/Makefile | 43 ++++++
> board/ti/am335x/common_def.h | 24 +++
> board/ti/am335x/evm.c | 50 +++++++
> board/ti/am335x/mux.c | 278 ++++++++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> drivers/serial/ns16550.c | 7 +-
> include/configs/am335x_evm.h | 121 ++++++++++++++++
> 9 files changed, 589 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/am33xx/board.c
> create mode 100644 board/ti/am335x/Makefile
> create mode 100644 board/ti/am335x/common_def.h
> create mode 100644 board/ti/am335x/evm.c
> create mode 100644 board/ti/am335x/mux.c
> create mode 100644 include/configs/am335x_evm.h
Also the MAINTAINERS file should be updated.
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 18+ messages in thread