[U-Boot] [PATCH v2 0/3] Remove duplicate functions for power and sleep configuration

[U-Boot] [PATCH v2 0/3] Remove duplicate functions for power and sleep configuration

[Christian Riesch]

Hi,
these patches apply on top of Heiko Schocher's patches for the enbw_cmc
board. They remove the duplicate functions for the power and sleep
controller of the davinci devices.

Changes for v2:
- use -M option of git format-patch to detect the renaming of files
- Removed one patch of the patchset (arm, davinci: Correct the MDSTAT.STATE
  mask) since a similar patch was already submitted by Sergei Shtylyov. 
  The prerequisites list below was updated accordingly.
- Use defines for bitmasks for PSC configuration instead of magic numbers.

The first patch renames the low level configuration functions since they can
not only be used for the AM1808 but for the entire da850 family.

Patch number two adds a function to set an LPSC module to Sync Reset
state as this is required for DDR memory controller initialization.

The third patch finally replaces the PSC related functions in
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c by those of psc.c.

I am looking forward to your comments!

Prerequisites:

[U-Boot] arm, post, memory: fix bug if sdram base != 0x00000000
http://patchwork.ozlabs.org/patch/118208/

[U-Boot] : davinci: Replace CONFIG_PRELOADER with CONFIG_SPL_BUILD in board/davinci/common/misc.c
http://patchwork.ozlabs.org/patch/114482/

[U-Boot] arm, fdt: update ethernet mac address before booting Linux
http://patchwork.ozlabs.org/patch/114736/

[U-Boot,v2] arm, logbuffer: make it compileclean
http://patchwork.ozlabs.org/patch/119183/

[U-Boot,v2] cosmetic, post: Codingstyle cleanup
http://patchwork.ozlabs.org/patch/119184/

[U-Boot] arm, post: add missing post_time_ms for arm
http://patchwork.ozlabs.org/patch/114743/

[U-Boot,v2,1/3] arm, davinci: fix typo in arch/arm/cpu/arm926ejs/davinci/Makefile
http://patchwork.ozlabs.org/patch/118310/

[U-Boot,v2,2/3] arm, davinci: add DAVINCI_MMC_CLKID
http://patchwork.ozlabs.org/patch/118309/

[U-Boot,v2,3/3] arm, davinci: add support for am1808 based enbw_cmc board
http://patchwork.ozlabs.org/patch/118311/

[U-Boot,v3] DaVinci: correct MDSTAT.STATE mask
http://patchwork.ozlabs.org/patch/116094/

Regards, Christian

Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

Christian Riesch (3):
  arm, davinci: Rename AM1808 lowlevel functions to DA850
  arm, davinci: Add function lpsc_syncreset()
  arm, davinci: Remove the duplication of LPSC functions in
    da850_lowlevel.c

 arch/arm/cpu/arm926ejs/davinci/Makefile            |    2 +-
 .../{am1808_lowlevel.c => da850_lowlevel.c}        |  202 ++++++--------------
 arch/arm/cpu/arm926ejs/davinci/psc.c               |   20 ++-
 .../{am1808_lowlevel.h => da850_lowlevel.h}        |   26 ++--
 arch/arm/include/asm/arch-davinci/hardware.h       |    2 +
 board/enbw/enbw_cmc/enbw_cmc.c                     |    2 +-
 include/configs/enbw_cmc.h                         |   92 +++++-----
 7 files changed, 135 insertions(+), 211 deletions(-)
 rename arch/arm/cpu/arm926ejs/davinci/{am1808_lowlevel.c => da850_lowlevel.c} (57%)
 rename arch/arm/include/asm/arch-davinci/{am1808_lowlevel.h => da850_lowlevel.h} (63%)

[U-Boot] [PATCH v2 1/3] arm, davinci: Rename AM1808 lowlevel functions to DA850

[Christian Riesch]

Rename arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c and
arch/arm/include/asm/arch-davinci/am1808_lowlevel.h to da850_lowlevel.c
and da850_lowlevel.h since they apply not only to the AM1808 SoC
but to all DA850 chips. The function names and #defines are changed
likewise.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 arch/arm/cpu/arm926ejs/davinci/Makefile            |    2 +-
 .../{am1808_lowlevel.c => da850_lowlevel.c}        |  136 ++++++++++----------
 .../{am1808_lowlevel.h => da850_lowlevel.h}        |   26 ++--
 board/enbw/enbw_cmc/enbw_cmc.c                     |    2 +-
 include/configs/enbw_cmc.h                         |   92 +++++++-------
 5 files changed, 129 insertions(+), 129 deletions(-)
 rename arch/arm/cpu/arm926ejs/davinci/{am1808_lowlevel.c => da850_lowlevel.c} (70%)
 rename arch/arm/include/asm/arch-davinci/{am1808_lowlevel.h => da850_lowlevel.h} (63%)

diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index d91a2b8..b2152df 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).o
 
 COBJS-y				+= cpu.o timer.o psc.o
-COBJS-$(CONFIG_AM1808_LOWLEVEL)       += am1808_lowlevel.o
+COBJS-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
 COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
 COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
similarity index 70%
rename from arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
rename to arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index 1ea4a9f..a6f0178 100644
--- a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -1,5 +1,5 @@
 /*
- * SoC-specific lowlevel code for AM1808 and similar chips
+ * SoC-specific lowlevel code for DA850
  *
  * Copyright (C) 2011
  * Heiko Schocher, DENX Software Engineering, hs at denx.de.
@@ -25,12 +25,12 @@
 #include <nand.h>
 #include <ns16550.h>
 #include <post.h>
-#include <asm/arch/am1808_lowlevel.h>
+#include <asm/arch/da850_lowlevel.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/ddr2_defs.h>
 #include <asm/arch/emif_defs.h>
 
-void am1808_waitloop(unsigned long loopcnt)
+void da850_waitloop(unsigned long loopcnt)
 {
 	unsigned long	i;
 
@@ -38,7 +38,7 @@ void am1808_waitloop(unsigned long loopcnt)
 		asm("   NOP");
 }
 
-int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
+int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 {
 	if (reg == davinci_pllc0_regs)
 		/* Unlock PLL registers. */
@@ -55,7 +55,7 @@ int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 	/* Set PLLEN=0 => PLL BYPASS MODE */
 	clrbits_le32(&reg->pllctl, 0x00000001);
 
-	am1808_waitloop(150);
+	da850_waitloop(150);
 
 	if (reg == davinci_pllc0_regs) {
 		/*
@@ -87,10 +87,10 @@ int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 
 	/* program the postdiv */
 	if (reg == davinci_pllc0_regs)
-		writel((0x8000 | CONFIG_SYS_AM1808_PLL0_POSTDIV),
+		writel((0x8000 | CONFIG_SYS_DA850_PLL0_POSTDIV),
 			&reg->postdiv);
 	else
-		writel((0x8000 | CONFIG_SYS_AM1808_PLL1_POSTDIV),
+		writel((0x8000 | CONFIG_SYS_DA850_PLL1_POSTDIV),
 			&reg->postdiv);
 
 	/*
@@ -101,17 +101,17 @@ int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 		;
 
 	if (reg == davinci_pllc0_regs) {
-		writel(CONFIG_SYS_AM1808_PLL0_PLLDIV1, &reg->plldiv1);
-		writel(CONFIG_SYS_AM1808_PLL0_PLLDIV2, &reg->plldiv2);
-		writel(CONFIG_SYS_AM1808_PLL0_PLLDIV3, &reg->plldiv3);
-		writel(CONFIG_SYS_AM1808_PLL0_PLLDIV4, &reg->plldiv4);
-		writel(CONFIG_SYS_AM1808_PLL0_PLLDIV5, &reg->plldiv5);
-		writel(CONFIG_SYS_AM1808_PLL0_PLLDIV6, &reg->plldiv6);
-		writel(CONFIG_SYS_AM1808_PLL0_PLLDIV7, &reg->plldiv7);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
 	} else {
-		writel(CONFIG_SYS_AM1808_PLL1_PLLDIV1, &reg->plldiv1);
-		writel(CONFIG_SYS_AM1808_PLL1_PLLDIV2, &reg->plldiv2);
-		writel(CONFIG_SYS_AM1808_PLL1_PLLDIV3, &reg->plldiv3);
+		writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
+		writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
+		writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
 	}
 
 	/*
@@ -128,13 +128,13 @@ int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 		;
 
 	/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
-	am1808_waitloop(200);
+	da850_waitloop(200);
 
 	/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
 	setbits_le32(&reg->pllctl, 0x00000008);
 
 	/* Wait for PLL to lock. See PLL spec for PLL lock time */
-	am1808_waitloop(2400);
+	da850_waitloop(2400);
 
 	/*
 	 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
@@ -153,7 +153,7 @@ int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 	return 0;
 }
 
-void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
+void da850_lpc_transition(unsigned char pscnum, unsigned char module,
 		unsigned char domain, unsigned char state)
 {
 	struct davinci_psc_regs	*reg;
@@ -190,12 +190,12 @@ void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
 		;
 }
 
-int am1808_ddr_setup(unsigned int freq)
+int da850_ddr_setup(unsigned int freq)
 {
 	unsigned long	tmp;
 
 	/* Enable the Clock to DDR2/mDDR */
-	am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
+	da850_lpc_transition(1, 6, 0, PSC_ENABLE);
 
 	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
@@ -217,19 +217,19 @@ int am1808_ddr_setup(unsigned int freq)
 		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
 	}
 
-	writel(CONFIG_SYS_AM1808_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
 	clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
 		(1 << DDR_SLEW_CMOSEN_BIT));
 
 	setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
 
-	writel((CONFIG_SYS_AM1808_DDR2_SDBCR & ~0xf0000000) |
+	writel((CONFIG_SYS_DA850_DDR2_SDBCR & ~0xf0000000) |
 		(readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
 		&dv_ddr2_regs_ctrl->sdbcr);
-	writel(CONFIG_SYS_AM1808_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+	writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
 
-	writel(CONFIG_SYS_AM1808_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
-	writel(CONFIG_SYS_AM1808_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 
 	clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
 		(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
@@ -238,15 +238,15 @@ int am1808_ddr_setup(unsigned int freq)
 	 * LPMODEN and MCLKSTOPEN must be set!
 	 * Without this bits set, PSC don;t switch states !!
 	 */
-	writel(CONFIG_SYS_AM1808_DDR2_SDRCR |
+	writel(CONFIG_SYS_DA850_DDR2_SDRCR |
 		(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
 		(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
 		&dv_ddr2_regs_ctrl->sdrcr);
 
 	/* SyncReset the Clock to EMIF3A SDRAM */
-	am1808_lpc_transition(1, 6, 0, PSC_SYNCRESET);
+	da850_lpc_transition(1, 6, 0, PSC_SYNCRESET);
 	/* Enable the Clock to EMIF3A SDRAM */
-	am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
+	da850_lpc_transition(1, 6, 0, PSC_ENABLE);
 
 	/* disable self refresh */
 	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
@@ -255,13 +255,13 @@ int am1808_ddr_setup(unsigned int freq)
 	return 0;
 }
 
-static void am1808_set_mdctl(dv_reg_p mdctl)
+static void da850_set_mdctl(dv_reg_p mdctl)
 {
 	if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
 		writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
 }
 
-void am1808_psc_init(void)
+void da850_psc_init(void)
 {
 	struct davinci_psc_regs	*reg;
 	int i;
@@ -272,10 +272,10 @@ void am1808_psc_init(void)
 		;
 
 	for (i = 3; i <= 4 ; i++)
-		am1808_set_mdctl(&reg->psc0.mdctl[i]);
+		da850_set_mdctl(&reg->psc0.mdctl[i]);
 
 	for (i = 7; i <= 12 ; i++)
-		am1808_set_mdctl(&reg->psc0.mdctl[i]);
+		da850_set_mdctl(&reg->psc0.mdctl[i]);
 
 	/* Do Always-On Power Domain Transitions */
 	setbits_le32(&reg->ptcmd, 0x00000001);
@@ -287,15 +287,15 @@ void am1808_psc_init(void)
 	while ((readl(&reg->ptstat) & 0x00000001))
 		;
 
-	am1808_set_mdctl(&reg->psc1.mdctl[3]);
-	am1808_set_mdctl(&reg->psc1.mdctl[6]);
+	da850_set_mdctl(&reg->psc1.mdctl[3]);
+	da850_set_mdctl(&reg->psc1.mdctl[6]);
 
 	/* UART1 + UART2 */
 	for (i = 12 ; i <= 13 ; i++)
-		am1808_set_mdctl(&reg->psc1.mdctl[i]);
+		da850_set_mdctl(&reg->psc1.mdctl[i]);
 
-	am1808_set_mdctl(&reg->psc1.mdctl[26]);
-	am1808_set_mdctl(&reg->psc1.mdctl[31]);
+	da850_set_mdctl(&reg->psc1.mdctl[26]);
+	da850_set_mdctl(&reg->psc1.mdctl[31]);
 
 	/* Do Always-On Power Domain Transitions */
 	setbits_le32(&reg->ptcmd, 0x00000001);
@@ -303,7 +303,7 @@ void am1808_psc_init(void)
 		;
 }
 
-void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
+void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
 	unsigned long value)
 {
 	clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
@@ -369,42 +369,42 @@ int arch_cpu_init(void)
 		((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) |	(1 << 16)));
 
 	/* System PSC setup - enable all */
-	am1808_psc_init();
+	da850_psc_init();
 
 	/* Setup Pinmux */
-	am1808_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX0);
-	am1808_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX1);
-	am1808_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX2);
-	am1808_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX3);
-	am1808_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX4);
-	am1808_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX5);
-	am1808_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX6);
-	am1808_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX7);
-	am1808_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX8);
-	am1808_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX9);
-	am1808_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX10);
-	am1808_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX11);
-	am1808_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX12);
-	am1808_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX13);
-	am1808_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX14);
-	am1808_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX15);
-	am1808_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX16);
-	am1808_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX17);
-	am1808_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX18);
-	am1808_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX19);
+	da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
+	da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
+	da850_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX2);
+	da850_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX3);
+	da850_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX4);
+	da850_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX5);
+	da850_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX6);
+	da850_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX7);
+	da850_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX8);
+	da850_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX9);
+	da850_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX10);
+	da850_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX11);
+	da850_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX12);
+	da850_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX13);
+	da850_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX14);
+	da850_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX15);
+	da850_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX16);
+	da850_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX17);
+	da850_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX18);
+	da850_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX19);
 
 	/* PLL setup */
-	am1808_pll_init(davinci_pllc0_regs, CONFIG_SYS_AM1808_PLL0_PLLM);
-	am1808_pll_init(davinci_pllc1_regs, CONFIG_SYS_AM1808_PLL1_PLLM);
+	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
+	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
 
 	/* GPIO setup */
 	board_gpio_init();
 
 	/* setup CSn config */
-	writel(CONFIG_SYS_AM1808_CS2CFG, &davinci_emif_regs->ab1cr);
-	writel(CONFIG_SYS_AM1808_CS3CFG, &davinci_emif_regs->ab2cr);
+	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
+	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
 
-	am1808_lpc_transition(1, 13, 0, PSC_ENABLE);
+	da850_lpc_transition(1, 13, 0, PSC_ENABLE);
 	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 
@@ -416,13 +416,13 @@ int arch_cpu_init(void)
 		(CONFIG_SYS_NS16550_COM1 + 0x30));
 #if defined(CONFIG_NAND_SPL)
 	puts("ddr init\n");
-	am1808_ddr_setup(132);
+	da850_ddr_setup(132);
 
 	puts("boot u-boot ...\n");
 
 	nand_boot();
 #else
-	am1808_ddr_setup(132);
+	da850_ddr_setup(132);
 	return 0;
 #endif
 }
diff --git a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
similarity index 63%
rename from arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
rename to arch/arm/include/asm/arch-davinci/da850_lowlevel.h
index 0bc7f76..22a92a3 100644
--- a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
+++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
@@ -1,5 +1,5 @@
 /*
- * SoC-specific lowlevel code for AM1808 and similar chips
+ * SoC-specific lowlevel code for DA850
  *
  * Copyright (C) 2011
  * Heiko Schocher, DENX Software Engineering, hs at denx.de.
@@ -21,24 +21,24 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#ifndef __AM1808_LOWLEVEL_H
-#define __AM1808_LOWLEVEL_H
+#ifndef __DA850_LOWLEVEL_H
+#define __DA850_LOWLEVEL_H
 
 /* NOR Boot Configuration Word Field Descriptions */
-#define AM1808_NORBOOT_COPY_XK(X)	((X - 1) << 8)
-#define AM1808_NORBOOT_METHOD_DIRECT	(1 << 4)
-#define AM1808_NORBOOT_16BIT		(1 << 0)
+#define DA850_NORBOOT_COPY_XK(X)	((X - 1) << 8)
+#define DA850_NORBOOT_METHOD_DIRECT	(1 << 4)
+#define DA850_NORBOOT_16BIT		(1 << 0)
 
 #define dv_maskbits(addr, val) \
 	writel((readl(addr) & val), addr)
 
-void am1808_waitloop(unsigned long loopcnt);
-int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
-void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
+void da850_waitloop(unsigned long loopcnt);
+int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
+void da850_lpc_transition(unsigned char pscnum, unsigned char module,
 		unsigned char domain, unsigned char state);
-int am1808_ddr_setup(unsigned int freq);
-void am1808_psc_init(void);
-void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
+int da850_ddr_setup(unsigned int freq);
+void da850_psc_init(void);
+void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
 	unsigned long value);
 
-#endif /* #ifndef __AM1808_LOWLEVEL_H */
+#endif /* #ifndef __DA850_LOWLEVEL_H */
diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
index c25d240..d649d43 100644
--- a/board/enbw/enbw_cmc/enbw_cmc.c
+++ b/board/enbw/enbw_cmc/enbw_cmc.c
@@ -43,7 +43,7 @@
 #include <asm/arch/sdmmc_defs.h>
 #include <asm/arch/timer_defs.h>
 #include <asm/io.h>
-#include <asm/arch/am1808_lowlevel.h>
+#include <asm/arch/da850_lowlevel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index 2c21147..bb44f93 100644
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -44,7 +44,7 @@
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_AM1808_LOWLEVEL
+#define CONFIG_DA850_LOWLEVEL
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_HOSTNAME		enbw_cmc
 #define CONFIG_DISPLAY_CPUINFO
@@ -336,30 +336,30 @@
 /* LowLevel Init */
 /* PLL */
 #define CONFIG_SYS_DV_CLKMODE		0
-#define CONFIG_SYS_AM1808_PLL0_POSTDIV	0
-#define CONFIG_SYS_AM1808_PLL0_PLLDIV1	0x8000
-#define CONFIG_SYS_AM1808_PLL0_PLLDIV2	0x8001
-#define CONFIG_SYS_AM1808_PLL0_PLLDIV3	0x8002 /* 150MHz */
-#define CONFIG_SYS_AM1808_PLL0_PLLDIV4	0x8003
-#define CONFIG_SYS_AM1808_PLL0_PLLDIV5	0x8002
-#define CONFIG_SYS_AM1808_PLL0_PLLDIV6	CONFIG_SYS_AM1808_PLL0_PLLDIV1
-#define CONFIG_SYS_AM1808_PLL0_PLLDIV7	0x8005
-
-#define CONFIG_SYS_AM1808_PLL1_POSTDIV	1
-#define CONFIG_SYS_AM1808_PLL1_PLLDIV1	0x8000
-#define CONFIG_SYS_AM1808_PLL1_PLLDIV2	0x8001
-#define CONFIG_SYS_AM1808_PLL1_PLLDIV3	0x8002
-
-#define CONFIG_SYS_AM1808_PLL0_PLLM	18	/* PLL0 -> 456 MHz */
-#define CONFIG_SYS_AM1808_PLL1_PLLM	24	/* PLL1 -> 300 MHz */
+#define CONFIG_SYS_DA850_PLL0_POSTDIV	0
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1	0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2	0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3	0x8002 /* 150MHz */
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4	0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5	0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6	CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7	0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV	1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1	0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2	0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3	0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM	18	/* PLL0 -> 456 MHz */
+#define CONFIG_SYS_DA850_PLL1_PLLM	24	/* PLL1 -> 300 MHz */
 
 /* DDR RAM */
-#define CONFIG_SYS_AM1808_DDR2_DDRPHYCR (0 | \
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (0 | \
 			(0x1 << 7)   | \
 			(0x1 << 6)   | \
 			(0x4 << 0))
 
-#define CONFIG_SYS_AM1808_DDR2_SDBCR (0 | \
+#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
 		  (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
 		  (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
 		  (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
@@ -371,12 +371,12 @@
 		  (0x2 << DV_DDR_SDCR_IBANK_SHIFT)		| \
 		  (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 
-#define CONFIG_SYS_AM1808_DDR2_SDBCR2 4 /* 13 row address bits */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
 
 /*
  * freq = 150MHz -> t = 7ns
  */
-#define CONFIG_SYS_AM1808_DDR2_SDTIMR (0 | \
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
 		(0x0d << 25) | /* tRFC = 105 105/7 = 15 - 1 = 0xd */ \
 		(1 << 22)  | /* tRP 15/7 = 2 - 1 = 1 */		\
 		(1 << 19)  | /* tRCD  15/7 = 2 - 1 = 1 */	\
@@ -390,7 +390,7 @@
 /*
  * freq = 150MHz -> t=7ns
  */
-#define CONFIG_SYS_AM1808_DDR2_SDTIMR2 (0 | \
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
 	(readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
 	(8 << 27)	| /* tRASMAX [(70us/7800ns)-1] */ \
 	(2 << 25)	| /* tXP = 2, tCKe = 3 -> 3 - 1 = 2 */ \
@@ -400,35 +400,35 @@
 	(0 << 5)	| /* tRTP = 7.5 7.5/7 = 1 - 1 = 0 */ \
 	(2 << 0))	/* tCKE = 3 -> 3 - 1 = 2 */
 
-#define CONFIG_SYS_AM1808_DDR2_SDRCR	0x00000407
+#define CONFIG_SYS_DA850_DDR2_SDRCR	0x00000407
 
 /*
  * with Pin Setup Utility from TI
  * missing GPIO pin setup
  */
-#define CONFIG_SYS_AM1808_PINMUX0	0x44448888
-#define CONFIG_SYS_AM1808_PINMUX1	0x48888884
-#define CONFIG_SYS_AM1808_PINMUX2	0x88888888
-#define CONFIG_SYS_AM1808_PINMUX3	0x88888888
-#define CONFIG_SYS_AM1808_PINMUX4	0x22222288
-#define CONFIG_SYS_AM1808_PINMUX5	0x11111111
-#define CONFIG_SYS_AM1808_PINMUX6	0x11818811
-#define CONFIG_SYS_AM1808_PINMUX7	0x11111811
-#define CONFIG_SYS_AM1808_PINMUX8	0x11111111
-#define CONFIG_SYS_AM1808_PINMUX9	0x11111111
-#define CONFIG_SYS_AM1808_PINMUX10	0x11111111
-#define CONFIG_SYS_AM1808_PINMUX11	0x11111111
-#define CONFIG_SYS_AM1808_PINMUX12	0x11111111
-#define CONFIG_SYS_AM1808_PINMUX13	0x88888800
-#define CONFIG_SYS_AM1808_PINMUX14	0x00000088
-#define CONFIG_SYS_AM1808_PINMUX15	0x00000000
-#define CONFIG_SYS_AM1808_PINMUX16	0x88888880
-#define CONFIG_SYS_AM1808_PINMUX17	0x88888888
-#define CONFIG_SYS_AM1808_PINMUX18	0x88022288
-#define CONFIG_SYS_AM1808_PINMUX19	0x08022228
-
-#define CONFIG_SYS_AM1808_CS2CFG	0x08624311
-#define CONFIG_SYS_AM1808_CS3CFG	0x04222310
+#define CONFIG_SYS_DA850_PINMUX0	0x44448888
+#define CONFIG_SYS_DA850_PINMUX1	0x48888884
+#define CONFIG_SYS_DA850_PINMUX2	0x88888888
+#define CONFIG_SYS_DA850_PINMUX3	0x88888888
+#define CONFIG_SYS_DA850_PINMUX4	0x22222288
+#define CONFIG_SYS_DA850_PINMUX5	0x11111111
+#define CONFIG_SYS_DA850_PINMUX6	0x11818811
+#define CONFIG_SYS_DA850_PINMUX7	0x11111811
+#define CONFIG_SYS_DA850_PINMUX8	0x11111111
+#define CONFIG_SYS_DA850_PINMUX9	0x11111111
+#define CONFIG_SYS_DA850_PINMUX10	0x11111111
+#define CONFIG_SYS_DA850_PINMUX11	0x11111111
+#define CONFIG_SYS_DA850_PINMUX12	0x11111111
+#define CONFIG_SYS_DA850_PINMUX13	0x88888800
+#define CONFIG_SYS_DA850_PINMUX14	0x00000088
+#define CONFIG_SYS_DA850_PINMUX15	0x00000000
+#define CONFIG_SYS_DA850_PINMUX16	0x88888880
+#define CONFIG_SYS_DA850_PINMUX17	0x88888888
+#define CONFIG_SYS_DA850_PINMUX18	0x88022288
+#define CONFIG_SYS_DA850_PINMUX19	0x08022228
+
+#define CONFIG_SYS_DA850_CS2CFG	0x08624311
+#define CONFIG_SYS_DA850_CS3CFG	0x04222310
 
 /*
  * NOR Bootconfiguration word:
-- 
1.7.0.4

[U-Boot] [PATCH v2 2/3] arm, davinci: Add function lpsc_syncreset()

[Christian Riesch]

This patch adds a function lpsc_syncreset that allows setting a
lpsc module into Sync Reset state.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 arch/arm/cpu/arm926ejs/davinci/psc.c         |   20 +++++++++++++++-----
 arch/arm/include/asm/arch-davinci/hardware.h |    2 ++
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c
index 707fa47..3e92518 100644
--- a/arch/arm/cpu/arm926ejs/davinci/psc.c
+++ b/arch/arm/cpu/arm926ejs/davinci/psc.c
@@ -46,7 +46,7 @@
  */
 
 /* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
+static void lpsc_transition(unsigned int id, unsigned int state)
 {
 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
 #ifdef CONFIG_SOC_DA8XX
@@ -83,10 +83,10 @@ void lpsc_on(unsigned int id)
 	while (readl(ptstat) & 0x01)
 		continue;
 
-	if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03)
-		return; /* Already on and enabled */
+	if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
+		return; /* Already in that state */
 
-	writel(readl(mdctl) | 0x03, mdctl);
+	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
 
 	switch (id) {
 #ifdef CONFIG_SOC_DM644X
@@ -114,10 +114,20 @@ void lpsc_on(unsigned int id)
 
 	while (readl(ptstat) & 0x01)
 		continue;
-	while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03)
+	while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
 		continue;
 }
 
+void lpsc_on(unsigned int id)
+{
+	lpsc_transition(id, 0x03);
+}
+
+void lpsc_syncreset(unsigned int id)
+{
+	lpsc_transition(id, 0x01);
+}
+
 /* Not all DaVinci chips have a DSP power domain. */
 #ifdef CONFIG_SOC_DM644X
 
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index a9c2839..26f17a3 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -291,6 +291,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #endif /* CONFIG_SOC_DA8XX */
 
 void lpsc_on(unsigned int id);
+void lpsc_syncreset(unsigned int id);
 void dsp_on(void);
 
 void davinci_enable_uart0(void);
@@ -357,6 +358,7 @@ struct davinci_psc_regs {
 #endif /* CONFIG_SOC_DA8XX */
 
 #define PSC_MDSTAT_STATE		0x3f
+#define PSC_MDCTL_NEXT			0x07
 
 #ifndef CONFIG_SOC_DA8XX
 
-- 
1.7.0.4

[U-Boot] [PATCH v2 3/3] arm, davinci: Remove the duplication of LPSC functions in da850_lowlevel.c

[Christian Riesch]

The LPSC functions defined in
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
are replaced by those already defined in
arch/arm/cpu/arm926ejs/davinci/psc.c.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c |   96 +----------------------
 1 files changed, 4 insertions(+), 92 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index a6f0178..490ef8f 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -153,49 +153,12 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 	return 0;
 }
 
-void da850_lpc_transition(unsigned char pscnum, unsigned char module,
-		unsigned char domain, unsigned char state)
-{
-	struct davinci_psc_regs	*reg;
-	dv_reg_p mdstat, mdctl;
-
-	if (pscnum == 0) {
-		reg = davinci_psc0_regs;
-		mdstat = &reg->psc0.mdstat[module];
-		mdctl = &reg->psc0.mdctl[module];
-	} else {
-		reg = davinci_psc1_regs;
-		mdstat = &reg->psc1.mdstat[module];
-		mdctl = &reg->psc1.mdctl[module];
-	}
-
-	/* Wait for any outstanding transition to complete */
-	while ((readl(&reg->ptstat) & (0x00000001 << domain)))
-		;
-
-	/* If we are already in that state, just return */
-	if ((readl(mdstat) & 0x1F) == state)
-		return;
-
-	/* Perform transition */
-	writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
-	setbits_le32(&reg->ptcmd, (0x00000001 << domain));
-
-	/* Wait for transition to complete */
-	while (readl(&reg->ptstat) & (0x00000001 << domain))
-		;
-
-	/* Wait and verify the state */
-	while ((readl(mdstat) & 0x1F) != state)
-		;
-}
-
 int da850_ddr_setup(unsigned int freq)
 {
 	unsigned long	tmp;
 
 	/* Enable the Clock to DDR2/mDDR */
-	da850_lpc_transition(1, 6, 0, PSC_ENABLE);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 
 	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
@@ -244,9 +207,9 @@ int da850_ddr_setup(unsigned int freq)
 		&dv_ddr2_regs_ctrl->sdrcr);
 
 	/* SyncReset the Clock to EMIF3A SDRAM */
-	da850_lpc_transition(1, 6, 0, PSC_SYNCRESET);
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
 	/* Enable the Clock to EMIF3A SDRAM */
-	da850_lpc_transition(1, 6, 0, PSC_ENABLE);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 
 	/* disable self refresh */
 	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
@@ -255,54 +218,6 @@ int da850_ddr_setup(unsigned int freq)
 	return 0;
 }
 
-static void da850_set_mdctl(dv_reg_p mdctl)
-{
-	if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
-		writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
-}
-
-void da850_psc_init(void)
-{
-	struct davinci_psc_regs	*reg;
-	int i;
-
-	/* PSC 0 domain 0 init */
-	reg = davinci_psc0_regs;
-	while ((readl(&reg->ptstat) & 0x00000001))
-		;
-
-	for (i = 3; i <= 4 ; i++)
-		da850_set_mdctl(&reg->psc0.mdctl[i]);
-
-	for (i = 7; i <= 12 ; i++)
-		da850_set_mdctl(&reg->psc0.mdctl[i]);
-
-	/* Do Always-On Power Domain Transitions */
-	setbits_le32(&reg->ptcmd, 0x00000001);
-	while (readl(&reg->ptstat) & 0x00000001)
-		;
-
-	/* PSC1, domain 1 init */
-	reg = davinci_psc1_regs;
-	while ((readl(&reg->ptstat) & 0x00000001))
-		;
-
-	da850_set_mdctl(&reg->psc1.mdctl[3]);
-	da850_set_mdctl(&reg->psc1.mdctl[6]);
-
-	/* UART1 + UART2 */
-	for (i = 12 ; i <= 13 ; i++)
-		da850_set_mdctl(&reg->psc1.mdctl[i]);
-
-	da850_set_mdctl(&reg->psc1.mdctl[26]);
-	da850_set_mdctl(&reg->psc1.mdctl[31]);
-
-	/* Do Always-On Power Domain Transitions */
-	setbits_le32(&reg->ptcmd, 0x00000001);
-	while (readl(&reg->ptstat) & 0x00000001)
-		;
-}
-
 void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
 	unsigned long value)
 {
@@ -368,9 +283,6 @@ int arch_cpu_init(void)
 	dv_maskbits(&davinci_syscfg_regs->suspsrc,
 		((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) |	(1 << 16)));
 
-	/* System PSC setup - enable all */
-	da850_psc_init();
-
 	/* Setup Pinmux */
 	da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
 	da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
@@ -404,7 +316,7 @@ int arch_cpu_init(void)
 	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
 	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
 
-	da850_lpc_transition(1, 13, 0, PSC_ENABLE);
+	lpsc_on(DAVINCI_LPSC_UART2);
 	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 
-- 
1.7.0.4

[U-Boot] [PATCH v2 1/3] arm, davinci: Rename AM1808 lowlevel functions to DA850

[Heiko Schocher]

Hello Christian,

Christian Riesch wrote:
> Rename arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c and
> arch/arm/include/asm/arch-davinci/am1808_lowlevel.h to da850_lowlevel.c
> and da850_lowlevel.h since they apply not only to the AM1808 SoC
> but to all DA850 chips. The function names and #defines are changed
> likewise.
> 
> Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  arch/arm/cpu/arm926ejs/davinci/Makefile            |    2 +-
>  .../{am1808_lowlevel.c => da850_lowlevel.c}        |  136 ++++++++++----------
>  .../{am1808_lowlevel.h => da850_lowlevel.h}        |   26 ++--
>  board/enbw/enbw_cmc/enbw_cmc.c                     |    2 +-
>  include/configs/enbw_cmc.h                         |   92 +++++++-------
>  5 files changed, 129 insertions(+), 129 deletions(-)
>  rename arch/arm/cpu/arm926ejs/davinci/{am1808_lowlevel.c => da850_lowlevel.c} (70%)
>  rename arch/arm/include/asm/arch-davinci/{am1808_lowlevel.h => da850_lowlevel.h} (63%)

Tested on the enbw_cmc board, so:

Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH v2 2/3] arm, davinci: Add function lpsc_syncreset()

[Heiko Schocher]

Hello Christian,

Christian Riesch wrote:
> This patch adds a function lpsc_syncreset that allows setting a
> lpsc module into Sync Reset state.
> 
> Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  arch/arm/cpu/arm926ejs/davinci/psc.c         |   20 +++++++++++++++-----
>  arch/arm/include/asm/arch-davinci/hardware.h |    2 ++
>  2 files changed, 17 insertions(+), 5 deletions(-)

Tested on the enbw_cmc board, so:

Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH v2 3/3] arm, davinci: Remove the duplication of LPSC functions in da850_lowlevel.c

[Heiko Schocher]

Hello Christian,

Christian Riesch wrote:
> The LPSC functions defined in
> arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
> are replaced by those already defined in
> arch/arm/cpu/arm926ejs/davinci/psc.c.
> 
> Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c |   96 +----------------------
>  1 files changed, 4 insertions(+), 92 deletions(-)

Tested on the enbw_cmc board, so:

Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany