[U-Boot] [PATCH 1/3] [v2] powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot

[U-Boot] [PATCH 1/3] [v2] powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot

[Timur Tabi]

Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
displays which of these is actually built, but it's inconsistent.  This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used.  Not only that, but each board includes code that displays
the message, so there is duplication.

So instead of displaying this message at boot time, the address map size
information is moved into the 'bdinfo' command.  The board-specific code is
deleted.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 board/freescale/corenet_ds/corenet_ds.c     |    4 ----
 board/freescale/mpc8536ds/mpc8536ds.c       |    7 +------
 board/freescale/mpc8572ds/mpc8572ds.c       |    6 +-----
 board/freescale/p1010rdb/p1010rdb.c         |    6 +-----
 board/freescale/p1022ds/p1022ds.c           |    8 ++------
 board/freescale/p1_p2_rdb/p1_p2_rdb.c       |    4 +---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |    8 +-------
 board/freescale/p2020ds/p2020ds.c           |    8 ++------
 board/freescale/p2041rdb/p2041rdb.c         |    4 ----
 common/cmd_bdinfo.c                         |    8 ++++++++
 10 files changed, 17 insertions(+), 46 deletions(-)

diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index b1eecc4..a33c936 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -62,10 +62,6 @@ int checkboard (void)
 	else
 		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
 
-#ifdef CONFIG_PHYS_64BIT
-	puts("36-bit Addressing\n");
-#endif
-
 	/* Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index c9f85c8..6d0bfde 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -68,12 +68,7 @@ int checkboard (void)
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	puts("Board: MPC8536DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf ("Sys ID: 0x%02x, "
+	printf("Board: MPC8536DS Sys ID: 0x%02x, "
 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 		in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index b20299e..33a02ba 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -45,11 +45,7 @@ int checkboard (void)
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	puts ("Board: MPC8572DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts ("(36-bit addrmap) ");
-#endif
-	printf ("Sys ID: 0x%02x, "
+	printf("Board: MPC8572DS Sys ID: 0x%02x, "
 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 		in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 03e9da1..7aa2117 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -165,11 +165,7 @@ int checkboard(void)
 	struct cpu_type *cpu;
 
 	cpu = gd->cpu;
-	printf("Board: %sRDB ", cpu->name);
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap)");
-#endif
-	puts("\n");
+	printf("Board: %sRDB\n", cpu->name);
 
 	return 0;
 }
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 456d9b0..aca30f3 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -56,12 +56,8 @@ int checkboard(void)
 {
 	u8 sw;
 
-	puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+	printf("Board: P1022DS Sys ID: 0x%02x, "
+	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 864b3ce..6418710 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -110,9 +110,7 @@ int checkboard (void)
 
 	cpu = gd->cpu;
 	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
-#ifdef CONFIG_PHYS_64BIT
-	puts ("(36-bit addrmap) \n");
-#endif
+
 	setbits_be32(&pgpio->gpdir, GPIO_DIR);
 
 /*
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4671128..abe087b 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -225,13 +225,7 @@ int checkboard(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u8 in, out, io_config, val;
 
-	printf("Board: %s ", CONFIG_BOARDNAME);
-
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf("CPLD: V%d.%d PCBA: V%d.0\n",
+	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
 		in_8(&cpld_data->cpld_rev_major) & 0x0F,
 		in_8(&cpld_data->cpld_rev_minor) & 0x0F,
 		in_8(&cpld_data->pcba_rev) & 0x0F);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index d3af6cf..e8d31a4 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -61,12 +61,8 @@ int checkboard(void)
 {
 	u8 sw;
 
-	puts("Board: P2020DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+	printf("Board: P2020DS Sys ID: 0x%02x, "
+	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 6461bd7..1eed67e 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -54,10 +54,6 @@ int checkboard(void)
 	sw = CPLD_READ(fbank_sel);
 	printf("vBank: %d\n", sw & 0x1);
 
-#ifdef CONFIG_PHYS_64BIT
-	puts("36-bit Addressing\n");
-#endif
-
 	/*
 	 * Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..12863f2 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -96,6 +96,14 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_str("pevfreq",		strmhz(buf, bd->bi_pevfreq));
 #endif
 
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+#ifdef CONFIG_PHYS_64BIT
+	puts("addressing  = 36-bit\n");
+#else
+	puts("addressing  = 32-bit\n");
+#endif
+#endif
+
 	print_eth(0);
 #if defined(CONFIG_HAS_ETH1)
 	print_eth(1);
-- 
1.7.3.4

[U-Boot] [PATCH 2/3] [v2] phylib: wait for TN2020 to achieve SERDES lane alignment at startup

[Timur Tabi]

Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.

Note that this process can take up to three seconds.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 drivers/net/phy/teranetics.c |   33 +++++++++++++++++++++++++++++++++
 1 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index a13b48c..9d9397a 100644
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -21,6 +21,7 @@
  *
  */
 #include <config.h>
+#include <common.h>
 #include <phy.h>
 
 #ifndef CONFIG_PHYLIB_10G
@@ -43,6 +44,38 @@ int tn2020_config(struct phy_device *phydev)
 
 int tn2020_startup(struct phy_device *phydev)
 {
+	unsigned int timeout = 5 * 1000; /* 5 second timeout */
+
+#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
+			       MDIO_PHYXS_LNSTAT_SYNC1 | \
+			       MDIO_PHYXS_LNSTAT_SYNC2 | \
+			       MDIO_PHYXS_LNSTAT_SYNC3 | \
+			       MDIO_PHYXS_LNSTAT_ALIGN)
+
+	/*
+	 * Wait for the XAUI-SERDES lanes to align first.  Under normal
+	 * circumstances, this can take up to three seconds.
+	 */
+	while (--timeout) {
+		int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
+		if (reg < 0) {
+			printf("TN2020: Error reading from PHY@"
+			       "address %u\n", phydev->addr);
+			break;
+		}
+		if ((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
+			break;
+		udelay(1000);
+	}
+	if (!timeout) {
+		/*
+		 * A timeout is bad, but it may not be fatal, so don't
+		 * return an error.  Display a warning instead.
+		 */
+		printf("TN2020: Timeout waiting for PHY at address %u to "
+		       "align.\n", phydev->addr);
+	}
+
 	if (phydev->port != PORT_FIBRE)
 		return gen10g_startup(phydev);
 
-- 
1.7.3.4

[U-Boot] [PATCH 3/3] [v2] powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)

[Timur Tabi]

The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes
should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |   10 ------
 board/freescale/corenet_ds/eth_p4080.c        |   42 ++++++++++++++++++++-----
 drivers/net/phy/teranetics.h                  |    1 +
 3 files changed, 35 insertions(+), 18 deletions(-)
 create mode 100644 drivers/net/phy/teranetics.h

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 07e58ed..89ed5b4 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -504,9 +504,6 @@ void fsl_serdes_init(void)
 	const char *srds_lpd_arg;
 	size_t arglen;
 #endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
-	enum srds_prtcl device;
-#endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 	int need_serdes_a001;	/* TRUE == need work-around for SERDES A001 */
 #endif
@@ -787,11 +784,4 @@ void fsl_serdes_init(void)
 			     SRDS_RSTCTL_SDPD);
 	}
 #endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
-	for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
-		if (is_serdes_configured(device))
-			__serdes_reset_rx(srds_regs, cfg, device);
-	}
-#endif
 }
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index d4657f7..1c22a4d 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -42,6 +42,10 @@
 #include "../common/fman.h"
 #include <asm/fsl_dtsec.h>
 
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
+#include "../../../drivers/net/phy/teranetics.h" /* for tn2020_driver.uid */
+#endif
+
 #define EMI_NONE	0xffffffff
 #define EMI_MASK	0xf0000000
 #define EMI1_RGMII	0x0
@@ -93,21 +97,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval)
 	return bus;
 }
 
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
 int board_phy_config(struct phy_device *phydev)
 {
-	/*
-	 * If this is the 10G PHY, and we switched it to fiber,
-	 * we need to reset the serdes link for SERDES9
-	 */
-	if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) {
+	if (phydev->drv->uid == tn2020_driver.uid) {
+		unsigned long timeout = 1 * 1000; /* 1 seconds */
 		enum srds_prtcl device;
 
+		/*
+		 * Wait for the XAUI to come out of reset.  This is when it
+		 * starts transmitting alignment signals.
+		 */
+		while (--timeout) {
+			int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
+			if (reg < 0) {
+				printf("TN2020: Error reading from PHY@"
+				       "address %u\n", phydev->addr);
+				break;
+			}
+			/*
+			 * Note that we've never actually seen
+			 * MDIO_CTRL1_RESET set to 1.
+			 */
+			if ((reg & MDIO_CTRL1_RESET) == 0)
+				break;
+			udelay(1000);
+		}
+
+		if (!timeout) {
+			printf("TN2020: Timeout waiting for PHY at address %u "
+			       " to reset.\n", phydev->addr);
+		}
+
 		switch (phydev->addr) {
-		case 4:
+		case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
 			device = XAUI_FM1;
 			break;
-		case 0:
+		case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
 			device = XAUI_FM2;
 			break;
 		default:
diff --git a/drivers/net/phy/teranetics.h b/drivers/net/phy/teranetics.h
new file mode 100644
index 0000000..1d983de
--- /dev/null
+++ b/drivers/net/phy/teranetics.h
@@ -0,0 +1 @@
+extern struct phy_driver tn2020_driver;
-- 
1.7.3.4

[U-Boot] [PATCH 3/3] [v2] powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)

[Kumar Gala]

On Oct 7, 2011, at 3:35 PM, Timur Tabi wrote:

> The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes
> should be reset after the XAUI starts tranmitting alignment signals.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |   10 ------
> board/freescale/corenet_ds/eth_p4080.c        |   42 ++++++++++++++++++++-----
> drivers/net/phy/teranetics.h                  |    1 +
> 3 files changed, 35 insertions(+), 18 deletions(-)
> create mode 100644 drivers/net/phy/teranetics.h
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
> index 07e58ed..89ed5b4 100644
> --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
> +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
> @@ -504,9 +504,6 @@ void fsl_serdes_init(void)
> 	const char *srds_lpd_arg;
> 	size_t arglen;
> #endif
> -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
> -	enum srds_prtcl device;
> -#endif
> #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
> 	int need_serdes_a001;	/* TRUE == need work-around for SERDES A001 */
> #endif
> @@ -787,11 +784,4 @@ void fsl_serdes_init(void)
> 			     SRDS_RSTCTL_SDPD);
> 	}
> #endif
> -
> -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
> -	for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
> -		if (is_serdes_configured(device))
> -			__serdes_reset_rx(srds_regs, cfg, device);
> -	}
> -#endif
> }
> diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
> index d4657f7..1c22a4d 100644
> --- a/board/freescale/corenet_ds/eth_p4080.c
> +++ b/board/freescale/corenet_ds/eth_p4080.c
> @@ -42,6 +42,10 @@
> #include "../common/fman.h"
> #include <asm/fsl_dtsec.h>
> 
> +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
> +#include "../../../drivers/net/phy/teranetics.h" /* for tn2020_driver.uid */
> +#endif
> +
> #define EMI_NONE	0xffffffff
> #define EMI_MASK	0xf0000000
> #define EMI1_RGMII	0x0
> @@ -93,21 +97,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval)
> 	return bus;
> }
> 
> -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
> +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
> int board_phy_config(struct phy_device *phydev)
> {
> -	/*
> -	 * If this is the 10G PHY, and we switched it to fiber,
> -	 * we need to reset the serdes link for SERDES9
> -	 */
> -	if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) {
> +	if (phydev->drv->uid == tn2020_driver.uid) {

Rather than looking at tn2020_driver.uid lets just do something like:

if ((phydev->drv->uid & phydev->drv->mask) == TN2020_UID)

And add a #define in phy.h:

#define TN2020_UID	0x00a19410

> +		unsigned long timeout = 1 * 1000; /* 1 seconds */
> 		enum srds_prtcl device;
> 
> +		/*
> +		 * Wait for the XAUI to come out of reset.  This is when it
> +		 * starts transmitting alignment signals.
> +		 */
> +		while (--timeout) {
> +			int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
> +			if (reg < 0) {
> +				printf("TN2020: Error reading from PHY at "
> +				       "address %u\n", phydev->addr);
> +				break;
> +			}
> +			/*
> +			 * Note that we've never actually seen
> +			 * MDIO_CTRL1_RESET set to 1.
> +			 */
> +			if ((reg & MDIO_CTRL1_RESET) == 0)
> +				break;
> +			udelay(1000);
> +		}
> +
> +		if (!timeout) {
> +			printf("TN2020: Timeout waiting for PHY at address %u "
> +			       " to reset.\n", phydev->addr);
> +		}
> +
> 		switch (phydev->addr) {
> -		case 4:
> +		case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
> 			device = XAUI_FM1;
> 			break;
> -		case 0:
> +		case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
> 			device = XAUI_FM2;
> 			break;
> 		default:
> diff --git a/drivers/net/phy/teranetics.h b/drivers/net/phy/teranetics.h
> new file mode 100644
> index 0000000..1d983de
> --- /dev/null
> +++ b/drivers/net/phy/teranetics.h
> @@ -0,0 +1 @@
> +extern struct phy_driver tn2020_driver;
> -- 
> 1.7.3.4
> 
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/3] [v2] powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot

[Kumar Gala]

On Oct 7, 2011, at 3:35 PM, Timur Tabi wrote:

> Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
> displays which of these is actually built, but it's inconsistent.  This is
> especially problematic since the "default" build for a given 85xx board can
> be either one, so if you don't see a message, you can't always know which
> size is being used.  Not only that, but each board includes code that displays
> the message, so there is duplication.
> 
> So instead of displaying this message at boot time, the address map size
> information is moved into the 'bdinfo' command.  The board-specific code is
> deleted.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> board/freescale/corenet_ds/corenet_ds.c     |    4 ----
> board/freescale/mpc8536ds/mpc8536ds.c       |    7 +------
> board/freescale/mpc8572ds/mpc8572ds.c       |    6 +-----
> board/freescale/p1010rdb/p1010rdb.c         |    6 +-----
> board/freescale/p1022ds/p1022ds.c           |    8 ++------
> board/freescale/p1_p2_rdb/p1_p2_rdb.c       |    4 +---
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |    8 +-------
> board/freescale/p2020ds/p2020ds.c           |    8 ++------
> board/freescale/p2041rdb/p2041rdb.c         |    4 ----
> common/cmd_bdinfo.c                         |    8 ++++++++
> 10 files changed, 17 insertions(+), 46 deletions(-)

For the FSL boards, lets add 'bdinfo' to 'preboot' and enable CONFIG_PREBOOT

> 
> diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
> index b1eecc4..a33c936 100644
> --- a/board/freescale/corenet_ds/corenet_ds.c
> +++ b/board/freescale/corenet_ds/corenet_ds.c
> @@ -62,10 +62,6 @@ int checkboard (void)
> 	else
> 		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
> 
> -#ifdef CONFIG_PHYS_64BIT
> -	puts("36-bit Addressing\n");
> -#endif
> -
> 	/* Display the RCW, so that no one gets confused as to what RCW
> 	 * we're actually using for this boot.
> 	 */
> diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
> index c9f85c8..6d0bfde 100644
> --- a/board/freescale/mpc8536ds/mpc8536ds.c
> +++ b/board/freescale/mpc8536ds/mpc8536ds.c
> @@ -68,12 +68,7 @@ int checkboard (void)
> 	u8 vboot;
> 	u8 *pixis_base = (u8 *)PIXIS_BASE;
> 
> -	puts("Board: MPC8536DS ");
> -#ifdef CONFIG_PHYS_64BIT
> -	puts("(36-bit addrmap) ");
> -#endif
> -
> -	printf ("Sys ID: 0x%02x, "
> +	printf("Board: MPC8536DS Sys ID: 0x%02x, "
> 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
> 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
> 		in_8(pixis_base + PIXIS_PVER));
> diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
> index b20299e..33a02ba 100644
> --- a/board/freescale/mpc8572ds/mpc8572ds.c
> +++ b/board/freescale/mpc8572ds/mpc8572ds.c
> @@ -45,11 +45,7 @@ int checkboard (void)
> 	u8 vboot;
> 	u8 *pixis_base = (u8 *)PIXIS_BASE;
> 
> -	puts ("Board: MPC8572DS ");
> -#ifdef CONFIG_PHYS_64BIT
> -	puts ("(36-bit addrmap) ");
> -#endif
> -	printf ("Sys ID: 0x%02x, "
> +	printf("Board: MPC8572DS Sys ID: 0x%02x, "
> 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
> 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
> 		in_8(pixis_base + PIXIS_PVER));
> diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
> index 03e9da1..7aa2117 100644
> --- a/board/freescale/p1010rdb/p1010rdb.c
> +++ b/board/freescale/p1010rdb/p1010rdb.c
> @@ -165,11 +165,7 @@ int checkboard(void)
> 	struct cpu_type *cpu;
> 
> 	cpu = gd->cpu;
> -	printf("Board: %sRDB ", cpu->name);
> -#ifdef CONFIG_PHYS_64BIT
> -	puts("(36-bit addrmap)");
> -#endif
> -	puts("\n");
> +	printf("Board: %sRDB\n", cpu->name);
> 
> 	return 0;
> }
> diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
> index 456d9b0..aca30f3 100644
> --- a/board/freescale/p1022ds/p1022ds.c
> +++ b/board/freescale/p1022ds/p1022ds.c
> @@ -56,12 +56,8 @@ int checkboard(void)
> {
> 	u8 sw;
> 
> -	puts("Board: P1022DS ");
> -#ifdef CONFIG_PHYS_64BIT
> -	puts("(36-bit addrmap) ");
> -#endif
> -
> -	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
> +	printf("Board: P1022DS Sys ID: 0x%02x, "
> +	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
> 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
> 
> 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
> diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
> index 864b3ce..6418710 100644
> --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
> +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
> @@ -110,9 +110,7 @@ int checkboard (void)
> 
> 	cpu = gd->cpu;
> 	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
> -#ifdef CONFIG_PHYS_64BIT
> -	puts ("(36-bit addrmap) \n");
> -#endif
> +
> 	setbits_be32(&pgpio->gpdir, GPIO_DIR);
> 
> /*
> diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> index 4671128..abe087b 100644
> --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> @@ -225,13 +225,7 @@ int checkboard(void)
> 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> 	u8 in, out, io_config, val;
> 
> -	printf("Board: %s ", CONFIG_BOARDNAME);
> -
> -#ifdef CONFIG_PHYS_64BIT
> -	puts("(36-bit addrmap) ");
> -#endif
> -
> -	printf("CPLD: V%d.%d PCBA: V%d.0\n",
> +	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
> 		in_8(&cpld_data->cpld_rev_major) & 0x0F,
> 		in_8(&cpld_data->cpld_rev_minor) & 0x0F,
> 		in_8(&cpld_data->pcba_rev) & 0x0F);
> diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
> index d3af6cf..e8d31a4 100644
> --- a/board/freescale/p2020ds/p2020ds.c
> +++ b/board/freescale/p2020ds/p2020ds.c
> @@ -61,12 +61,8 @@ int checkboard(void)
> {
> 	u8 sw;
> 
> -	puts("Board: P2020DS ");
> -#ifdef CONFIG_PHYS_64BIT
> -	puts("(36-bit addrmap) ");
> -#endif
> -
> -	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
> +	printf("Board: P2020DS Sys ID: 0x%02x, "
> +	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
> 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
> 
> 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
> diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
> index 6461bd7..1eed67e 100644
> --- a/board/freescale/p2041rdb/p2041rdb.c
> +++ b/board/freescale/p2041rdb/p2041rdb.c
> @@ -54,10 +54,6 @@ int checkboard(void)
> 	sw = CPLD_READ(fbank_sel);
> 	printf("vBank: %d\n", sw & 0x1);
> 
> -#ifdef CONFIG_PHYS_64BIT
> -	puts("36-bit Addressing\n");
> -#endif
> -
> 	/*
> 	 * Display the RCW, so that no one gets confused as to what RCW
> 	 * we're actually using for this boot.
> diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
> index 6051120..12863f2 100644
> --- a/common/cmd_bdinfo.c
> +++ b/common/cmd_bdinfo.c
> @@ -96,6 +96,14 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> 	print_str("pevfreq",		strmhz(buf, bd->bi_pevfreq));
> #endif
> 
> +#ifdef CONFIG_ENABLE_36BIT_PHYS
> +#ifdef CONFIG_PHYS_64BIT
> +	puts("addressing  = 36-bit\n");
> +#else
> +	puts("addressing  = 32-bit\n");
> +#endif
> +#endif
> +
> 	print_eth(0);
> #if defined(CONFIG_HAS_ETH1)
> 	print_eth(1);
> -- 
> 1.7.3.4
> 
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/3] [v2] powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)

[Tabi Timur-B04825]

Kumar Gala wrote:
> Rather than looking at tn2020_driver.uid lets just do something like:
>
> if ((phydev->drv->uid&  phydev->drv->mask) == TN2020_UID)
>
> And add a #define in phy.h:
>
> #define TN2020_UID	0x00a19410

I guess that makes more sense.  I thought my original version was cooler, 
though.

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot] [PATCH 1/3] [v2] powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot

[Tabi Timur-B04825]

Kumar Gala wrote:
> For the FSL boards, lets add 'bdinfo' to 'preboot' and enable CONFIG_PREBOOT

I don't think that's a good idea.  bdinfo display about a dozen lines of 
text, most of it is not generally useful.  Plus, this would make preboot 
unavailable for everyone else.

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot] [PATCH 2/3] [v2] phylib: wait for TN2020 to achieve SERDES lane alignment at startup

[Kumar Gala]

On Oct 7, 2011, at 3:35 PM, Timur Tabi wrote:

> Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
> aligned, so wait for lane alignment before completing the startup sequence.
> 
> Note that this process can take up to three seconds.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> drivers/net/phy/teranetics.c |   33 +++++++++++++++++++++++++++++++++
> 1 files changed, 33 insertions(+), 0 deletions(-)

applied to 85xx

- k