[U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01

Stefano Babic
2011-10-14T11:04:33Z

On 10/14/2011 10:05 AM, Helmut Raiger wrote:
> This adds basic board support for TT-01 based on
> the bluetechnix i.MX31 SOM. Currently only NOR-Flash
> boot is implemented.
>
> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
> ---
>
> V2:
> - MAINTAINER updated and used board.cfg instead of Makefile change
> - eliminated config.mk
> - replaced __REG accessors (WEIM and ESD),
> this patch depends on http://patchwork.ozlabs.org/patch/116978/
> - MACH_TYPE_TT01 setup standardized
> - removed dependency on mx31pdk low level code
> - reduced lowlevel_init.S to its minimum (AIPS setup only), moved
> DDR and clock setup to board_early_init_f()
> - some mulitiline comment cosmetics
> - added some comments to clarify the board setup
> (SYS_MONITOR_LEN, SYS_MALLOC_LEN)
> - removed definition of CONFIG_SYS_GBL_DATA_SIZE
>
> MAINTAINERS | 4 +
> board/hale/tt01/Makefile | 51 ++++++++
> board/hale/tt01/lowlevel_init.S | 32 +++++
> board/hale/tt01/tt01.c | 187 +++++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/tt01.h | 249 +++++++++++++++++++++++++++++++++++++++
> 6 files changed, 524 insertions(+), 0 deletions(-)
> create mode 100644 board/hale/tt01/Makefile
> create mode 100644 board/hale/tt01/lowlevel_init.S
> create mode 100644 board/hale/tt01/tt01.c
> create mode 100644 include/configs/tt01.h
>

> diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
> new file mode 100644
> index 0000000..ecade40
> --- /dev/null
> +++ b/board/hale/tt01/tt01.c
> @@ -0,0 +1,187 @@
> +/*
> + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
> + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <command.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define BOARD_STRING "Board: HALE TT-01"
> +
> +/* Clock configuration */
> +#define CCM_CCMR_SETUP 0x074B0BF5
> +
> +static void board_setup_clocks(void)
> +{
> + struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
> + volatile int wait = 0x10000;
> +
> + writel(CCM_CCMR_SETUP, &ccm->ccmr);
> + while (wait--) ;

I had the same problem - a udelay() before relocation.

However, there is a sdelay() in armv7 (syslib.c), and I sent a patch to
move this stuff into arm/lib to make this and the other functions
available to all ARM SOCs

http://patchwork.ozlabs.org/patch/114909/

Albert, what do you think about ?

> +/* DRAM configuration */
> +
> +#define ESDMISC_MDDR_SETUP 0x00000004
> +#define ESDMISC_MDDR_RESET_DL 0x0000000c
> +/*
> + * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
> + * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
> + * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
> + * tRCD = 011, tRC = 010
> + * note: all but tWTR (1), tRC (111) are reset defaults,
> + * the same values work in the jtag configuration
> + *
> + * Bluetechnix setup has 0x75e73a (for 128MB) =
> + * 0b 0111 0101 1110 0111 0011 1010
> + * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
> + * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
> + * tRCD = 011, tRC = 010
> + */

Ok, values are good explained !

> +static void board_setup_sdram(void)
> +{
> + u32 *pad;
> + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
> +
> + /*
> + * setup pad control for the controller pins
> + * no loopback, no pull, no keeper, no open drain,
> + * standard input, standard drive, slow slew rate
> + */
> + for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
> + pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
> + *pad = 0;
> +
> + /* set up MX31 DDR Memory Controller */
> + writel(ESDMISC_MDDR_SETUP, &esdc->misc);
> + writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
> +
> + /* perform DDR init sequence for CSD0 */
> + writel(ESDCTL_PRECHARGE, &esdc->ctl0);
> + writel(0x12344321, CSD0_BASE+0x0f00);
> + writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
> + writel(0x12344321, CSD0_BASE);
> + writel(0x12344321, CSD0_BASE);
> + writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
> + writeb(0xda, CSD0_BASE+0x33);
> + writeb(0xff, CSD0_BASE+0x1000000);
> + writel(ESDCTL_RW, &esdc->ctl0);
> + writel(0xDEADBEEF, CSD0_BASE);
> + writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);

I have supposed that the last thing to do is to set the ctl0 register to
normal mode, and that is. I wonder that you issue at the end a DL_RESET,
but I do not know your RAM. It is in any case different as explained in
manual (19.4.5.6).

> +
> + /* this seems essential, won't start without, but why? */
> + writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);

I cannot help - It seems related to yiour board, because I have not seen
the same issue on other i.MX31 targets.

> +
> +int checkboard(void)
> +{
> + printf(BOARD_STRING "\n");

Replace with "puts".

> +/* MC13783 connected to CSPI3 and SS0 */
> +#define CONFIG_FSL_PMIC

There are changes for PMIC. There is now a common PMIC core to support
PMICs from different manufacturers, not only Freescale. The old driver
is dropped - I sent patches to adapt the current boards, and I have
merged them on u-boot-imx. Not yet pulled, but with the old driver your
board will not be built.

You need to set (instead of CONFIG_FSL_PMIC):

#define CONFIG_PMIC
#define CONFIG_PMIC_SPI
#define CONFIG_PMIC_FSL

> +#define CONFIG_FSL_PMIC_BUS 2
> +#define CONFIG_FSL_PMIC_CS 0
> +#define CONFIG_FSL_PMIC_CLK 1000000
> +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)

These are ok - special SPI setup have maintained the name.

Best regards,
Stefano Babic

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