[U-Boot] [PATCH] FIX for dcache_disable() for ARM926ej-s

[Sergei Shtylyov <sshtylyov@mvista.com>]

Hello.

On 21-10-2011 10:44, Bas van den Berg wrote:

> the cache also needs to be invalidated, not just flushed, Since re-enabling it,
> can cause inconsistent data without invalidation. See example below.

> in c-file:
> static int num = 1;

> void test() {
>      num = 1;
>      dcache_enable();
>      printf("Cache on, num=%d\n", num);
>      num = 2;
>      dcache_disable();
>      printf("Cache off, num=%d\n", num);
>      num = 1;
>      dcache_enable();
>      printf("Cache on, num=%d\n", num);  // ->  prints 2 instead of 1!!
>      dcache_disable();
>      printf("Cache off, num=%d\n", num);
> }
> ---
>   arch/arm/lib/cache.c |    2 ++
>   1 files changed, 2 insertions(+), 0 deletions(-)

> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
> index b545fb7..10eb8c9 100644
> --- a/arch/arm/lib/cache.c
> +++ b/arch/arm/lib/cache.c
> @@ -37,6 +37,8 @@ void  __flush_cache(unsigned long start, unsigned long size)
>   	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
>   	/* disable write buffer as well (page 2-22) */
>   	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
> +    /* Invalidate dcache as well */
> +    asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));

    Please indent with tabs as above.

WBR, Sergei